Cacheline Marking for Store Reordering in Processor Memory Systems
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Solution Overview
Problem
The disparity between microprocessor clock speeds and memory access speeds leads to significant performance issues due to the inability to effectively reorder non-consecutive store operations to the same cacheline, which restricts memory bandwidth reduction and complicates store queue design.
Innovation Solution
A system that facilitates store reordering through cacheline marking, where a store-mark is set by a thread to allow exclusive access and merging of consecutive and non-consecutive stores to the same cacheline, maintaining the Total-Store-Order memory model by using a private buffer and cache-coherence mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If non-consecutive stores to the same cacheline are kept in program order in the store queue, then memory model integrity is maintained, but memory bandwidth is not reduced and processor performance deteriorates
Solution Approach 1:
The patent applies preliminary action by setting a store-mark bit on the cacheline before merging non-consecutive stores. This pre-marking allows the store queue to identify and merge stores that can be reordered without violating memory model semantics, enabling performance optimization while maintaining correctness through the预先 established marking mechanism
Solution Approach 2:
The store-mark bit serves as an intermediary mechanism between the store queue and memory ordering requirements. It provides a signaling mechanism that allows the store queue to safely reorder stores by indicating which cachelines have been exclusively stored to, enabling reordering decisions without complex dependency analysis while preserving memory model integrity
2Loss of energy
If stores are merged into a single entry in the store queue, then memory bandwidth usage is reduced, but the ability to maintain program order for non-consecutive stores is lost
Solution Approach 1:
The patent applies local quality by setting the store-mark bit specifically on cachelines that have been exclusively stored to, rather than globally. This localized marking allows selective merging of stores only where it is safe to do so, preserving program order where required while enabling bandwidth optimization where possible, thus maintaining memory model compliance while reducing memory traffic
3Reliability
If the store queue maintains ordering information for all stores, then memory model integrity is preserved, but device complexity increases
Solution Approach 1:
The patent extracts the ordering information requirement by using the store-mark bit to identify stores that can be merged and reordered. Instead of maintaining full ordering information for all stores, the system only needs to track the store-mark status, significantly simplifying the store queue design while preserving memory model integrity for stores that require ordering
Data Source
AI summary
One embodiment of the present invention provides a system that facilitates store reordering through cacheline marking. During operation, the system receives a memory operation which is directed to a cacheline. Next, the system determines whether a thread which is performing the memory operation has set a store-mark for the cacheline. If the thread has set the store-mark for the cacheline, the system performs the memory operation. Otherwise, the system determines if the cacheline has been store-marked by another thread. If so, the system delays the memory operation. On the other hand, if the cacheline has not been store-marked by another thread, the system performs the memory operation.