Caching Bridge Architecture Preventing Snoop Conflicts

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Solution Overview

Problem

Prior art multi-core processors and computer systems face cache access conflicts due to the limitations of inclusive cache structures, such as last level caches (LLCs), which increase as the number of processor cores or agents grows, leading to performance degradation.

Innovation Solution

The implementation of a caching bridge architecture with cache bridge scheduling and ordering (CBSO) logic that manages and prevents conflicts by using internal and external request queues to handle cache accesses, including speculative snoop blocking mechanisms to prevent conflicts between external agent snoops and cross-snoops within a multi-core processor system.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If an inclusive cache structure (LLC) is used to service cache requests from multiple agents, then cache access conflicts are reduced, but snoop conflicts between external agents and cross-snoops increase as the number of cores increases

Engineering Contradiction:
Improvecache access efficiencyVSAvoidsnoop conflict management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

A snoop blocking mechanism is introduced as an intermediary between external agents and the LLC. This mechanism intercepts and blocks external snoop requests during critical periods when cross-snoops are in progress, preventing conflicts without requiring changes to the core cache architecture or snoop logic

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system performs preliminary detection of cross-snoop conditions before external snoops can occur. By detecting when a cross-snoop is in progress and proactively blocking external snoop requests in advance, the system prevents conflicts before they can arise, rather than resolving them after occurrence

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If the number of processor cores or agents is increased, then system capability is improved, but the number of potential snoop conflicts increases

Engineering Contradiction:
Improvesystem scalabilityVSAvoidcache access reliability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The snoop management function is segmented into separate handling paths for external agents and cross-core requests. The snoop blocking mechanism creates a distinct control path that independently manages external snoop requests, separating them from the internal cross-snoop operations. This segmentation allows the system to scale to more cores without proportionally increasing conflict complexity

Inventive Principle:
Principle #1Segmentation

3Device complexity

If cache conflicts are allowed to occur, then system simplicity is maintained, but processor performance degrades due to multiple processing cycles required for conflict resolution

Engineering Contradiction:
Improvecache management simplicityVSAvoidprocessor performance
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The snoop blocking mechanism acts as an intermediary that prevents conflicts before they degrade performance. By blocking external snoops during cross-snoop operations, the system eliminates the need for complex conflict resolution processing cycles, maintaining simple cache management logic while preserving processor performance

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS7689778B2Preventing system snoop and cross-snoop conflicts
Publication Date: 2010.03.30 TAHOE RES LTD
  • US7689778B2 patent drawing
  • US7689778B2 patent drawing
  • US7689778B2 patent drawing

AI summary

In various embodiments, hardware, software and firmware or combinations thereof may be used to prevent cache conflicts within microprocessors and/or computer systems. More particularly, embodiments of the invention relate to a technique to prevent cache conflicts within a processor and/or computer system in which a number of accesses may be made to a particular cache or group of caches.