Caching Network Fabric for HPC Data Transport

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Solution Overview

Problem

High-performance computing (HPC) systems face performance bottlenecks due to the need to choose between scale-out and scale-up designs, which limits application performance and increases system management complexity, especially when handling large memory and computational operations.

Innovation Solution

An improved network fabric that enables coherent data sharing between computing nodes using RDMA and cache coherence engines, allowing for optimal data transport modes (scale-out or scale-up) based on workflow requirements, and integrating these capabilities into a single integrated circuit package to eliminate kernel intervention and support flexible data access across nodes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If scale-out design is used to network many commodity computing devices, then system size and memory capacity increase, but application performance deteriorates due to kernel processing bottlenecks

Engineering Contradiction:
Improvememory capacityVSAvoidapplication performance
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The patent extracts the kernel processing function from the data path by implementing RDMA (Remote Direct Memory Access) technology. This allows data to be transferred directly between remote memory locations without passing through the operating system kernel, eliminating the kernel processing bottleneck while maintaining scale-out architecture benefits.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces an intermediary mechanism (RDMA engine and cache coherence engine) that mediates between the application and remote memory. This intermediary handles the complex memory access and coherence protocols, allowing applications to access remote memory as if it were local memory without kernel intervention.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If scale-up design is used with RDMA and cache coherence, then application performance improves, but system complexity and management difficulty increase

Engineering Contradiction:
Improveapplication performanceVSAvoidsystem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges RDMA functionality and cache coherence functionality into a single integrated network fabric interface. This integration reduces the number of separate components and simplifies system management while maintaining the performance benefits of both technologies.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent creates a universal network fabric interface that can operate in multiple modes (RDMA mode and cache coherence mode) depending on the application requirements. This multi-functionality allows the same hardware infrastructure to support both scale-out and scale-up paradigms without increasing overall system complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Speed

If RDMA is implemented for direct memory access, then data transport efficiency improves, but adaptability to different application types deteriorates

Engineering Contradiction:
Improvedata transport efficiencyVSAvoidapplication compatibility
Core Design Contradiction:
SpeedVSAdaptability or versatility

Solution Approach 1:

The patent implements a dynamic selection mechanism that allows the system to switch between RDMA mode and cache coherence mode based on application requirements. This dynamic adaptability enables the same infrastructure to optimize for speed when using RDMA or for coherence when using cache protocols, accommodating different application types.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10404800B2Caching network fabric for high performance computing
Publication Date: 2019.09.03 HEWLETT PACKARD ENTERPRISE DEV LP
  • US10404800B2 patent drawing
  • US10404800B2 patent drawing
  • US10404800B2 patent drawing

AI summary

An apparatus and method exchange data between two nodes of a high performance computing (HPC) system using a data communication link. The apparatus has one or more processing cores, RDMA engines, cache coherence engines, and multiplexers. The multiplexers may be programmed by a user application, for example through an API, to selectively couple either the RDMA engines, cache coherence engines, or a mix of these to the data communication link. Bulk data transfer to the nodes of the HPC system may be performed using paged RDMA during initialization. Then, during computation proper, random access to remote data may be performed using a coherence protocol (e.g. MESI) that operates on much smaller cache lines.