Calculation Processing Apparatus Store Load Order Control
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Solution Overview
Problem
Conventional processors face performance issues due to incorrect data retrieval when executing instruction strings that store data in a cache line before loading from the same line, leading to out-of-order execution of store and load instructions, which can result in reexecution of instructions and decreased performance.
Innovation Solution
A calculation processing apparatus with a cache memory, decoder, storing device, and inhibitor that determines whether the storing device can afford to store memory access instructions and inhibits the execution of subsequent instructions if not, ensuring data consistency by maintaining the order of store and load operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If out-of-order execution is implemented to enhance calculator efficiency, then instruction processing efficiency is improved, but data consistency is compromised leading to wrong data retrieval
Solution Approach 1:
The LDSTQ manager performs preliminary actions by checking whether a store instruction is present before allowing load instruction execution. This advance verification prevents the harmful effect of reading data before the store instruction completes, while still allowing out-of-order execution to proceed when safe.
Solution Approach 2:
The LDSTQ manager acts as an intermediary between the out-of-order execution mechanism and the data consistency requirement. It monitors the execution state of store instructions and mediates the load instruction execution accordingly, allowing efficiency while preventing data consistency violations.
2Speed
If load instructions are executed before store instructions complete, then processing speed is improved, but incorrect data is returned as a result
Solution Approach 1:
The LDSTQ manager implements feedback by continuously monitoring the execution state of store instructions and using this information to control load instruction execution. When a store instruction is detected, the manager provides feedback to prevent premature load execution, ensuring data accuracy while maintaining high processing speed when data is ready.
3Reliability
If reexecution is performed to correct data consistency errors, then data accuracy is improved, but performance is largely affected due to time consumption
Solution Approach 1:
The LDSTQ manager applies preliminary anti-action by preventing the occurrence of data consistency errors in the first place through advance checking of store instruction presence. This proactive approach eliminates the need for subsequent reexecution operations, avoiding time loss while maintaining data consistency.
Solution Approach 2:
The system provides beforehand cushioning by implementing protective checks that prevent harmful reexecution scenarios. The LDSTQ manager's monitoring mechanism cushions against potential data consistency violations before they can occur, eliminating the need for corrective reexecution operations.
4Reliability
If the LDSTQ waits for antecedent instruction issuance to maintain order, then data consistency is preserved, but out-of-order execution performance benefit is invalidated
Solution Approach 1:
The LDSTQ manager implements dynamics by adapting the execution order based on real-time conditions. When store instructions are present, it dynamically adjusts to maintain proper ordering; when store instructions are absent, it allows out-of-order execution to proceed, achieving both reliability and productivity.
Data Source
AI summary
By including a storing device that stores a plurality of memory access instructions decoded by a decoder and outputs the memory access instruction stored therein to a cache memory, a determiner that determines whether the storing device is afford to store the plurality of memory access instructions; and an inhibitor that inhibits, when the determiner determines that the storing device is not afford to store a first memory access instruction included in the plurality of memory access instructions, execution of a second memory access instruction being included in the plurality of memory access instructions and being subsequent to the first memory access instruction for a predetermined time period, regardless of a result of determination made on the second memory access instruction by the determiner, the calculation processing apparatus inhibits a switch of the order of a store instruction and a load instruction.