Calculation System With Selective Address Circuit For Upper K Signal Extraction
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Solution Overview
Problem
Existing calculation systems face inefficiencies in processing and addressing signals generated from arithmetic operations, particularly in identifying and utilizing the upper K values among multiple signals, which hampers their effective utilization and scalability.
Innovation Solution
A calculation system comprising a crossbar array configuration with multiplying and adding elements, a processing circuit, and an address solution circuit that selectively enables address circuits based on upper flag values, allowing for efficient identification and utilization of upper K signals in parallel processing, thereby reducing the number of cycles required for address solution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional calculation system processes multiple signals from arithmetic operations, then all signals are generated and available, but the system cannot efficiently identify and utilize only the upper K values among them
Solution Approach 1:
The calculation system is segmented into distinct functional modules: a crossbar array for parallel arithmetic operations, an upper value detection circuit for identifying upper K values, and an address solution circuit for locating these values. This segmentation allows each module to specialize in its function, improving overall efficiency while managing complexity through modular design
Solution Approach 2:
The system performs preliminary detection of upper K values immediately after arithmetic operations complete, before full signal processing begins. The upper value detection circuit identifies which signals contain the upper K values in advance, allowing subsequent address solution and data retrieval to focus only on relevant signals, thus improving productivity
2Measurement precision
If the system processes all signals generated from arithmetic operations, then complete data is available, but the number of cycles required for address solution increases
Solution Approach 1:
The system extracts only the essential information needed for address solution by detecting upper K values and their corresponding addresses, rather than processing all signal data. The address solution circuit is configured to operate exclusively on the subset of signals identified as containing upper K values, reducing the number of cycles required while maintaining identification accuracy
Solution Approach 2:
The upper value detection circuit performs preliminary identification of upper K values and their addresses before the address solution phase begins. This preliminary action filters the signal set, allowing the address solution circuit to work with a reduced subset of relevant signals, thereby reducing processing cycles without sacrificing accuracy
3Productivity
If the calculation system processes a large number of signals in parallel, then processing capacity increases, but power consumption increases
Solution Approach 1:
The parallel processing system is segmented into active and inactive portions through the upper value detection mechanism. Only the circuit components and signal paths corresponding to upper K values remain active during address solution, while other parallel processing elements can enter low-power states, thus maintaining parallel processing capacity while reducing overall power consumption
Solution Approach 2:
The system performs partial action by focusing computational resources only on identifying and processing the upper K values among all generated signals. Rather than fully activating all parallel processing paths for complete signal analysis, the system activates only the necessary portion corresponding to upper K values, reducing power consumption while maintaining productivity for the most critical data
Data Source
AI summary
According to one embodiment, in a calculation system, a plurality of multiplying elements is arrayed to form a plurality of rows and a plurality of columns and are configured to multiply a plurality of first signals by respective weights to generate a plurality of calculation results and are configured to calculate a sum of calculation results in each column among the plurality of calculation results to generate a plurality of second signals individually for the plurality of columns. A first processing circuit is configured to receive the plurality of second signals generated by the adding elements, and to extract values corresponding to certain second signals among the plurality of second signals. A second processing circuit including a plurality of address circuits corresponding to the plurality of second signals, and configured to selectively enable address circuits corresponding to the certain second signals among the plurality of address circuits.