Calibrated Comparator Circuits for Parallel Analog Test Buses
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Solution Overview
Problem
Analog-test-bus apparatuses face inefficiencies due to the risk of accidental shorting and inaccuracies in comparator circuits, which are either imprecise and large or small and imprecise, leading to issues with parasitic noise and ground bounce, affecting the measurement of multiple circuit nodes simultaneously.
Innovation Solution
The use of a digital-to-analog converter (DAC) to drive comparator circuits with differential reference lines and data storage and logic circuitry to provide calibration data for adjusting comparison operations, mitigating inaccuracies and enabling precise measurement of multiple circuit nodes in parallel by accounting for offset and gain errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If comparator circuits are made small to increase the number of testable nodes, then productivity improves, but measurement precision deteriorates due to imprecision and noise
Solution Approach 1:
The patent applies preliminary action by performing calibration of comparator circuits before actual testing operations. Calibration data is obtained in advance and stored in memory, allowing the imprecise small comparators to be corrected for offset and gain errors prior to use. This enables the system to maintain measurement precision while using small comparators for high-productivity parallel testing of multiple circuit nodes.
2Productivity
If multiple circuit nodes are tested simultaneously to improve efficiency, then productivity improves, but the risk of accidental shorting and noise interference increases
Solution Approach 1:
The patent applies segmentation by dividing the testing function into separate comparator circuits for each circuit node, with each comparator independently connected to its designated node. This segmentation allows simultaneous testing of multiple nodes while isolating potential shorting risks to individual comparators rather than affecting the entire system. The calibration approach further segments the error correction process, applying individual calibration data to each comparator to eliminate noise and offset errors independently.
3Device complexity
If comparator circuits are made imprecise to reduce area, then device complexity decreases, but manufacturing precision deteriorates
Solution Approach 1:
The patent applies self-service by implementing a calibration system where each comparator circuit serves itself through individual calibration. Calibration data is obtained for each comparator by applying test signals and measuring outputs, then storing this data in memory. During operation, each comparator uses its own calibration data to correct its measurements, enabling imprecise small comparators to achieve the precision of larger comparators without increasing area or complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for precise and efficient testing of multiple circuit nodes by calibrating comparator circuits using calibration data, reducing the risk of shorting and noise interference, and improving the accuracy of transfer functions, thereby enhancing the reliability and efficiency of analog-test-bus systems.
Implementation Method 1
at least one digital-to-analog converter (DAC) configured and arranged to drive the input ports of the plurality of comparator circuits
Data Source
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AI summary
An example analog-test-bus (ATB) apparatus includes a plurality of comparator circuits, each having an output port, and a pair of input ports of opposing polarity including an inverting port and a non-inverting port, a plurality of circuit nodes to be selectively connected to the input ports of a first polarity, and at least one digital-to-analog converter (DAC) to drive the input ports of the plurality of comparator circuits. The apparatus further includes data storage and logic circuitry that accounts for inaccuracies attributable to the plurality of comparator circuits by providing, for each comparator circuit, a set of calibration data indicative of the inaccuracies for adjusting comparison operations performed by the plurality of comparator circuits.