Calibrated Delay Lines for Programmable Phase Shifts in Frequency Dividers
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Solution Overview
Problem
Existing solutions for generating 90-degree phase shifts in frequency dividers are inefficient, lack precision, or consume excessive power and chip area, making them unsuitable for certain applications.
Innovation Solution
The implementation of calibrated delay lines with a phase detector unit and digital calibration logic to generate accurate and programmable phase delay output signals, allowing for arbitrary phase differences beyond 90 degrees.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple phase-locked loops are used to generate various frequencies, then the necessary phase shift can be achieved, but power consumption increases and chip area becomes larger
Solution Approach 1:
The patent combines multiple frequency divider unit cells into a single integrated structure that generates multiple output frequencies simultaneously. By merging the functionality of multiple PLLs into one unified circuit with shared resources, the design achieves the same phase shift capabilities while reducing overall power consumption and chip area.
Solution Approach 2:
The frequency divider unit cell is designed to perform multiple functions: it can divide frequencies by different odd values (3, 5, 7, etc.) and generate multiple output phases (0, 120, 240 degrees) from a single structure. This multi-functionality eliminates the need for separate dedicated circuits for each frequency division ratio, thereby reducing power consumption and area.
2Measurement precision
If multiple phase-locked loops are used to generate various frequencies, then the necessary phase shift can be achieved, but chip area becomes larger
Solution Approach 1:
The patent combines multiple frequency divider unit cells into a single integrated structure that generates multiple output frequencies simultaneously. By merging the functionality of multiple PLLs into one unified circuit with shared resources, the design achieves the same phase shift capabilities while reducing overall power consumption and chip area.
Solution Approach 2:
The frequency divider unit cell employs a nested structure where common sub-circuits (such as phase detectors, charge pumps, and VCOs) are shared across multiple division ratios. The unit cell is designed so that internal components are reused and nested within each other, maximizing area efficiency while maintaining the ability to generate multiple frequency outputs.
3Measurement precision
If mixer-based phase shifters are used, then the necessary phase shift can be generated, but amplitude variations are introduced and power consumption increases
Solution Approach 1:
The patent replaces mixer-based phase shifting (which relies on analog multiplication and signal mixing) with a digital frequency division approach. By using sequential logic circuits and digital signal processing instead of analog mixers, the design eliminates amplitude variations while reducing power consumption and simplifying the overall system architecture.
4Measurement precision
If RC phase shift networks are used, then accurate phase shifts can be provided, but signal losses increase at higher frequencies
Solution Approach 1:
The patent replaces RC phase shift networks (analog passive components) with active digital frequency division circuits. This substitution eliminates the frequency-dependent signal losses inherent in RC networks by using regenerative digital logic that maintains signal strength across a wide frequency range, thereby improving high-frequency performance.
Data Source
AI summary
A system and a method are disclosed for generating accurate and programmable phase delay output signals, including a phase detector unit configured to determine a phase disparity signal based on a phase error between outputs of a frequency divider unit cell; a digital calibration logic unit configured to generate a control signal based on the phase disparity signal; and a tunable delay lines unit configured to generate the phase delay output signals based on the control signal.