Calibrated Droop Detection Circuit for IC Timing Protection
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Solution Overview
Problem
Integrated circuits (ICs) fail to meet timing requirements when supply voltage drops below a threshold, leading to inefficiencies and suboptimal design due to the lack of effective droop detection and compensation.
Innovation Solution
A droop detector system utilizing N-bit time-to-digital converters with adjustable miller capacitances to detect the magnitude and duration of supply voltage droops, enabling high-resolution monitoring and timely corrective actions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the IC is designed with a tolerance level for supply voltage drops, then the IC can operate reliably under varying voltage conditions, but the IC fails to meet timing requirements and operates suboptimally when voltage drops occur
Solution Approach 1:
The droop detector is configured to detect supply voltage drops before they cause timing failures. By monitoring voltage droops in real-time and generating early warnings, the system enables preventive actions to be taken before the voltage drop affects IC timing requirements, thus maintaining both reliability and precision
Solution Approach 2:
The system implements a feedback mechanism where the droop detector continuously monitors supply voltage and provides information about voltage droops to the control logic. This feedback loop enables the system to adjust its operation or trigger corrective measures based on detected droops, preventing timing failures while maintaining optimal performance
2Reliability
If the IC is designed to meet timing requirements under worst-case voltage conditions, then the IC operates reliably, but the design becomes suboptimal and inefficient under normal operating conditions
Solution Approach 1:
The system dynamically adjusts IC operation based on detected supply voltage conditions. When droops are detected, the system transitions to a conservative mode that ensures timing requirements are met. When no droops are present, the system operates in an optimized mode that maximizes performance and efficiency, thus resolving the contradiction between reliability and productivity
Solution Approach 2:
The droop detector enables the system to change operational parameters based on supply voltage conditions. By detecting voltage droops and adjusting timing margins, clock frequencies, or power management settings accordingly, the system maintains timing compliance under worst-case conditions while optimizing performance under normal conditions
3Device complexity
If traditional voltage monitoring methods are used, then the system is simple to implement, but the detection resolution and accuracy of voltage droops is insufficient
Solution Approach 1:
The time-to-digital converter is segmented into multiple units, each responsible for detecting specific time intervals corresponding to different droop magnitudes. This segmentation allows the system to achieve high-resolution detection of voltage droops by dividing the measurement range into discrete, manageable segments, improving precision without requiring a completely complex system architecture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables rapid and precise detection of supply voltage droops, allowing for quick corrective measures to maintain optimal IC performance under varying conditions, thus preventing timing failures.
Implementation Method 1
A capacitance associated with at least a subset of the N time-to-digital converter units is adjusted during a calibration time
Data Source
AI summary
A droop detector includes a phase generator generating a pulse responsive to a clock signal; an edge detector generating a first signal in response to the pulse; and a time-to-digital converter that includes N time-to-digital converter units. The time-to-digital converter generates an N-bit value representative of the timing difference between the edge of the pulse and the first signal. A capacitance associated with a subset of the time-to-digital converter units is adjusted during a calibration time to cause the difference between the arrival times of the data and clock at the jth time-to-digital converter unit to be greater than the difference between arrival times of the data and clock at the (j+1)th time-to-digital convert unit. The data terminal of the flip-flop of each time-to-digital converter unit is responsive to the first pulse, and the clock terminal of the flip-flop of each time-to-digital converter unit is responsive to the first signal.