Calibrated PLL Clock Signal Locking for High-Speed Data
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Solution Overview
Problem
Implementing high-speed communication protocols like GPON in programmable logic devices is challenging due to long dead time and multiple phase shifts, which cause the clock data recovery circuit to fail in locking to the incoming clock signal within a short period, leading to data loss and inaccurate sampling.
Innovation Solution
A calibrated phase-locked loop circuit is used to align the clock signals with the incoming data stream, employing a calibration control circuit to adjust the phases of clock outputs based on preamble bits, ensuring timely locking and accurate data sampling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a clock data recovery circuit is used to recover a clock signal from an incoming data stream, then the programmable device can communicate with external components, but the circuit cannot lock to the incoming clock signal within a relatively short period of time, causing long dead time and data loss
Solution Approach 1:
The patent applies preliminary action by using preamble bits at the beginning of each data frame to pre-calibrate the clock signal before actual data transmission occurs. The calibration circuit adjusts the clock signal phase and frequency in advance based on the preamble bits, enabling the clock data recovery circuit to lock quickly when the actual data stream arrives, thereby reducing dead time and preventing data loss.
2Adaptability or versatility
If different components send data at different phases even though they operate at the same frequency, then the programmable device can receive data from multiple external components, but information is lost because incoming data cannot be accurately sampled
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the clock signal phase and frequency parameters based on the received preamble bits. The calibration circuit modifies these parameters to match the phase and frequency characteristics of the incoming data stream from different external components, enabling accurate sampling regardless of the component's operating phase while maintaining the ability to receive data from multiple components.
Data Source
AI summary
Circuits and techniques for operating an integrated circuit are disclosed. A disclosed method includes receiving a data packet with a first operating frequency rate with first and second receiver circuits. The data packet may include a plurality of preamble bits. The first and second receiver circuits may operate at second and third operating frequency rates, respectively. A portion of the data packet received at the first receiver circuit is transmitted to a control circuit. The plurality of preamble bits within the portion of the data packet is identified with the control circuit. A clock circuit is then calibrated based on the plurality of preamble bits. The first and second receiver circuits may be clocked with first and second clock outputs from the clock circuit.