Calibrated Time-to-Digital Converter for Linear DPLL Output
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Solution Overview
Problem
Time-to-digital converters introduce nonlinearity into digital phase-locked loop circuits due to nonlinearity from analog-digital converters and multi-phase mismatches caused by ring oscillators, affecting the accuracy of digital code generation.
Innovation Solution
A time-to-digital converter design that includes a phase frequency detector, ring oscillator, counter array, multiplexer, analog-to-digital converter, calibrator, and adders to generate calibrated digital outputs by using offset lookup tables and gain correction to offset errors and nonlinearities, thereby improving the resolution and linearity of the digital phase-locked loop circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If an analog-to-digital converter is used to improve the resolution of the time-to-digital converter, then measurement precision is improved, but nonlinearity is introduced into the digital code output
Solution Approach 1:
The patent implements a feedback mechanism where the digital code output from the ADC is fed back to an error correction circuit. This circuit compares the actual output with the expected linear output and generates correction signals to compensate for nonlinearity. The feedback loop continuously adjusts the output to maintain linearity while preserving the high resolution provided by the ADC.
Solution Approach 2:
The patent changes the operating parameters of the ADC by applying variable offset voltages and gain adjustments based on calibration data. Different regions of the ADC's transfer function are compensated with different parameters to achieve overall linearity. This allows the system to maintain both high resolution and linearity across the full measurement range.
2Adaptability or versatility
If a ring oscillator is used to generate multi-phase clocks for time measurement, then measurement capability is improved, but multi-phase mismatch causes nonlinearity in the output
Solution Approach 1:
The patent performs preliminary calibration of the ring oscillator phases before actual measurement operations. During calibration, the system measures the actual phase offsets of each clock phase and stores correction values. These pre-determined correction values are then applied during normal operation to compensate for phase mismatches, ensuring accurate multi-phase measurements without introducing nonlinearity.
Solution Approach 2:
The patent divides the measurement range into multiple segments, each corresponding to a specific phase region. Within each segment, dedicated correction parameters are applied to compensate for phase-specific nonlinearity. This segmentation allows targeted correction of phase mismatch errors while maintaining the versatility of multi-phase operation across the entire measurement range.
Data Source
AI summary
Provided is a time-to-digital converter, comprising a phase frequency detector configured to receive a phase-locked loop input clock and a feedback clock, a ring oscillator configured to perform oscillation with multi-phase clocks of a first period, a counter array configured to count the number of oscillations in which the ring oscillator oscillates in a first period by the number of positive integers during the first pulse width, a multiplexer configured to divide the first period into a plurality of zones using edge information of the multi-phase clocks of the ring oscillator, and selects and outputs voltage information of a plurality of neighboring phase clocks included in a first zone from the plurality of zones, an analog-to-digital converter, a calibrator, and a first adder, wherein the calibrator comprises, an offset lookup table generation circuit, a gain-corrected analog-to-digital conversion output generator, and a second adder.