Calibrating Comparator SAR ADC Without Reference Voltage
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Solution Overview
Problem
Traditional Successive Approximation Analog to Digital Converters (SAR ADCs) face challenges with high power consumption and large chip area due to the need for capacitors with excellent linearity and the use of a reference voltage output unit, which increases power consumption and occupies more space.
Innovation Solution
A novel ADC architecture that utilizes a calibrating comparator and a look-up memory to perform accurate analog-to-digital conversion without requiring capacitors with excellent linearity and eliminates the need for a reference voltage, using a metal-dioxide-semiconductor capacitor structure to reduce chip area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If MIMC structure capacitors are used to ensure excellent linearity, then measurement precision is improved, but area of stationary object increases
Solution Approach 1:
The patent uses a calibration process to create a lookup table that copies the non-linear characteristics of MOSC capacitors into calibration data. This allows the system to compensate for non-linearity without requiring physically linear capacitors, thus using smaller MOSC capacitors instead of larger MIMC capacitors.
Solution Approach 2:
The patent changes the operating parameters by introducing calibration voltages and using a lookup table stored in memory. The calibration process characterizes the actual capacitance values at different voltage levels, and this characterization data is used to correct subsequent measurements, allowing the use of MOSC capacitors with acceptable rather than excellent linearity.
2Stability of the object's composition
If reference voltage output unit is added to provide stable reference voltage, then stability of the object's composition is improved, but use of energy by stationary object increases
Solution Approach 1:
The system uses itself to provide the reference function by utilizing the calibration data stored in the lookup table. Instead of requiring an external reference voltage source, the calibrated capacitor values stored in memory serve as the reference, eliminating the need for a separate reference voltage output unit and its associated power consumption.
Solution Approach 2:
The patent extracts the reference voltage function from a separate hardware unit and integrates it into the calibration data stored in memory. The lookup table contains pre-characterized capacitance values that serve as reference points, removing the need for an active reference voltage generation circuit.
3Reliability
If reference voltage output unit is added to provide stable reference voltage, then reliability is improved, but area of stationary object increases
Solution Approach 1:
The patent merges the reference voltage generation function with the calibration data storage in the lookup table. The same memory structure that stores calibration data also serves as the reference for conversions, eliminating the need for separate reference voltage hardware and reducing overall chip area while maintaining reliability through software-based reference management.
4Area of stationary object
If MOSC structure capacitors are used to reduce chip area, then area of stationary object is reduced, but measurement precision worsens
Solution Approach 1:
The patent implements a feedback mechanism where the actual non-linear characteristics of MOSC capacitors are measured during calibration and stored in a lookup table. This feedback information is then used to correct subsequent measurements, allowing the system to achieve high precision despite using non-linear MOSC capacitors.
Solution Approach 2:
The calibration process copies the non-linear voltage-capacitance characteristics of the MOSC capacitors into the lookup table. This digital copy of the physical non-linearity allows the system to mathematically compensate for it, achieving accurate measurements with smaller MOSC capacitors instead of requiring physically linear MIMC capacitors.
Data Source
AI summary
An analog-to-digital converter includes a sample and hold unit, a successive control unit, a look-up memory, and a calibrating comparator, which further includes a positive input end, a negative input end, a timing signal input end, a data port, a latch unit, an enable switch, a first controllable resistor, a second controllable resistor, a reset switch assembly, a controllable capacitive device, and an output end.