Calibration Data Generation Circuit for OCV Parameter Adjustment
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Solution Overview
Problem
Existing digital circuit simulation methods face inaccuracies due to conservative or relaxed on-chip variation (OCV) parameters provided by wafer foundries or designers, leading to potential increases in chip costs or functionality issues.
Innovation Solution
A calibration data generation circuit and method that ranks test points, performs scan shift operations, and adjusts the default timing derate factor based on comparison results between simulated and real-world hold time violations, using a scan chain design with a delay unit and scan flip-flops to achieve optimal test coverage and reasonable resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conservative on-chip variation (OCV) parameters are used in simulation, then chip reliability is improved, but chip cost increases
Solution Approach 1:
The patent adjusts the timing derate factor parameter from its default conservative value to an optimized value based on actual chip measurement data. By changing this parameter, the simulation results better match real-world performance, allowing designers to achieve reliable chip operation without overly conservative (and expensive) design margins.
2Ease of manufacture
If relaxed on-chip variation (OCV) parameters are used in simulation, then chip cost is reduced, but chip functionality may fail
Solution Approach 1:
The patent implements a feedback mechanism where actual chip measurement data (hold time violation data) is collected and used to calibrate the timing derate factor. This feedback loop ensures that the simulation parameters are continuously refined to match real-world behavior, preventing both over-design and under-design scenarios.
Solution Approach 2:
The patent performs preliminary calibration of the timing derate factor using measurement data from actual chips before final design decisions are made. This preliminary action allows designers to know the actual performance characteristics early in the design process, avoiding costly redesigns or functionality issues later.
3Device complexity
If default timing derate factor is used without calibration, then design process is simplified, but simulation accuracy deteriorates
Solution Approach 1:
The patent enables the simulation model to self-calibrate using measurement data from actual chips. The calibration process automatically adjusts the timing derate factor based on real-world data, making the simulation system self-improving without requiring complex external intervention or manual tuning.
Data Source
AI summary
The present application discloses a calibration data generation circuit and an associated method. The calibration data generation circuit includes: a first delay unit, having a first delay amount; and a first scan path, including: a first scan flip-flop, including: a scan data input terminal; a clock input terminal, arranged for receiving a clock signal; and an output terminal; and a second scan flip-flop, including: a scan data input terminal, coupled to the output terminal of the first scan flip-flop; a clock input terminal, arranged for receiving a delayed clock signal formed by the clock signal passing through the first delay unit; and an output terminal; wherein when the calibration data generation circuit operates, the first scan flip-flop and the second scan flip-flop are configured in a scan shift mode.