Calibration Device for Picosecond Timing Alignment in ATE

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current automated test systems (ATE) face challenges in achieving precise timing calibration, particularly in the picosecond range, due to measurement errors associated with methods like time domain reflectometry and robotic calibration, which are not effective at the device under test (DUT) location, and require external equipment and time-consuming socket removal.

Innovation Solution

A calibration device with multiple circuit paths connected to a common node, allowing signals to pass through and back through different paths, enabling precise timing alignment of test system channels to within five picoseconds without removing the DUT socket, using a resistive divider network and variable delay elements to adjust channel timing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If time domain reflectometry or robotic calibration is used for timing calibration, then calibration can be performed, but measurement precision is insufficient to achieve picosecond-level timing accuracy

Engineering Contradiction:
Improvetiming measurement precisionVSAvoidcalibration accuracy
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent introduces an intermediary calibration device with known delay characteristics that mediates between the test system channels and the DUT. This calibration device includes reference delay elements with precisely known delay values, allowing the system to measure and adjust channel timing skews by comparing signals through these known references, thereby achieving picosecond-level timing accuracy that cannot be obtained through direct TDR or robotic calibration methods.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If probing at the socket landing pattern is used for calibration, then timing can be measured, but the socket must be removed which increases loss of time and causes wear

Engineering Contradiction:
Improvetiming measurement capabilityVSAvoidcalibration time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The calibration device is designed to be inserted into the DUT socket in place of the actual device under test, allowing calibration to be performed preliminarily before actual testing. The calibration device includes built-in reference delay elements and circuit paths that enable timing measurements to be taken while the socket remains installed, eliminating the need for repeated socket removal and insertion during calibration procedures.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If external equipment such as probes and cables is used for calibration, then calibration can be performed, but device complexity increases

Engineering Contradiction:
Improvecalibration capabilityVSAvoidcalibration system complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent merges the calibration functionality directly into a compact device that fits within the DUT socket. The calibration device integrates multiple circuit paths, reference delay elements, and signal routing within a single package, eliminating the need for external probes, cables, and test instruments. This consolidation reduces device complexity while maintaining calibration precision, as the calibration functions are unified into one self-contained unit.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9164158B2Calibration device
Publication Date: 2015.10.20 TERADYNE INC
  • US9164158B2 patent drawing
  • US9164158B2 patent drawing
  • US9164158B2 patent drawing

AI summary

An example apparatus is for use in calibration of a test system having multiple channels and a socket for receiving a device under test. The example apparatus includes a device interface that is connectable to the socket; and multiple circuit paths, where each circuit path is connectable, through the device interface, to a corresponding channel of the test system and being connected to a common node. The example apparatus is configured so that, during calibration, signals either (i) each pass from the test system, through one of the multiple circuit paths, and back to the test system through others of the multiple circuit paths, or (ii) each pass from the test system, through the others of the multiple circuit paths, and back to the test system through the one of the multiple circuit paths.