Validating Call Stack Frames via Control Flow Tracing

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Solution Overview

Problem

Current solutions fail to accurately identify and correct improper information in call stacks due to operating system context switching, leading to unreliable hardware-based call stacks when multiple threads share a processor core.

Innovation Solution

The system employs static analysis of binaries to validate control flow routes between 'from' and 'to' addresses in call stacks, tracing routes from 'to' addresses to 'from' addresses to determine the validity of call stack frames and remove improper information by invalidating frames where such routes cannot be traced.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If hardware-based call stacks are used to collect performance data, then data collection speed is improved, but reliability deteriorates due to context switching causing improper information in call stacks

Engineering Contradiction:
Improvedata collection speedVSAvoidcall stack reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system performs preliminary validation of call stack frames by checking control flow routes before using the data for performance analysis. This prevents unreliable data from context switching from corrupting the analysis results, while maintaining the high-speed hardware-based collection approach

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary validation layer between the hardware call stack collection and the performance analysis tools. This intermediary checks whether control flow routes exist between consecutive frames, filtering out improper information caused by context switching while preserving legitimate high-speed data collection

Inventive Principle:
Principle #24Intermediary (Mediator)

2Power

If multiple threads share a processor core to increase processing power, then system throughput is improved, but measurement precision deteriorates due to unreliable call stack information

Engineering Contradiction:
Improvesystem throughputVSAvoidcall stack accuracy
Core Design Contradiction:
PowerVSMeasurement precision

Solution Approach 1:

The system uses feedback from control flow route validation to identify and exclude unreliable call stack frames. By checking whether a valid control flow route exists between consecutive frames, the system can distinguish between legitimate multi-threaded execution and context switching artifacts, maintaining measurement precision while allowing multiple threads to share cores

Inventive Principle:
Principle #23Feedback

3Reliability

If call stacks are validated using control flow route tracing, then reliability is improved, but device complexity increases due to additional validation requirements

Engineering Contradiction:
Improvecall stack validityVSAvoidvalidation system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts only the essential validation check - determining whether a control flow route exists between consecutive call stack frames. By focusing on this single critical validation rather than comprehensive analysis, the system achieves improved reliability without excessive complexity increase

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS11461220B2Techniques to identify improper information in call stacks
Publication Date: 2022.10.04 INTEL CORP
  • US11461220B2 patent drawing
  • US11461220B2 patent drawing
  • US11461220B2 patent drawing

AI summary

Embodiments are disclosed for obtaining a call stack for binaries, where the call stack includes a sequence of frames, and each frame has a “from” address and a “to” address for a call instruction, and for determining basic blocks of instructions for the binaries, where each basic block of instruction has one or more instructions. Further, the embodiments include traversing the call stack to validate from/to address pairs of sequential frames based on control flow routes existing between “from” addresses and “to” addresses of the from/to address pairs, where each from/to address pair has a “from” address of a frame and a “to” address of an immediate previous frame on the call stack.