Content Addressable Memory Without In-Cell Comparators
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The bus connection between memory arrays and central processing units (CPUs) acts as a bottleneck, limiting the increased speed of operation due to slower bus speeds compared to CPU speeds, despite advancements in CPU performance.
Innovation Solution
A content-addressable memory (CAM) unit is introduced without in-cell comparator circuitry, comprising a memory array, multiple row decoder, controller, and output unit, allowing for simultaneous activation of multiple rows and columns to perform Boolean operations within the memory array, thereby eliminating the need for a bus to move data for processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is stored in memory arrays and processed by CPU via bus connection, then data storage capacity is improved, but processing speed is limited by bus speed
Solution Approach 1:
The patent merges the memory array and processing functions into a single integrated structure. The memory array performs Boolean operations directly on stored data using column lines and word lines, eliminating the need for separate CPU processing through bus connections. This integration resolves the speed bottleneck by allowing processing to occur in parallel within the memory structure itself.
Solution Approach 2:
The patent transitions from sequential processing (data movement through bus) to parallel processing by utilizing the two-dimensional array structure of memory cells. Multiple rows and columns can be activated simultaneously, enabling massively parallel Boolean operations on multiple data elements at once, thus dramatically increasing processing speed while maintaining storage capacity.
2Quantity of substance
If traditional memory array with CPU processing is used, then data storage is achieved, but bus connection acts as bottleneck
Solution Approach 1:
The memory array becomes self-sufficient by incorporating the ability to perform processing operations directly within its structure. The array can execute Boolean operations on stored data without requiring external CPU intervention through bus connections, effectively serving both storage and processing functions autonomously and eliminating the productivity bottleneck.
3Measurement precision
If in-cell comparator circuitry is added to CAM unit, then matching accuracy is improved, but device complexity increases
Solution Approach 1:
The patent makes the memory array multi-functional by enabling it to perform both data storage and pattern matching operations. By utilizing the inherent Boolean logic capabilities of the memory cell structure (where intersection of activated rows and columns naturally produces match results), the system achieves accurate pattern matching without requiring separate comparator circuitry, thus maintaining simplicity while achieving the desired functionality.
Data Source
AI summary
A content addressable memory (CAM) unit does not have any in-cell comparator circuitry. The CAM unit includes a memory array, a multiple row decoder, a controller and an output unit. The memory array has storage cells arranged as data rows and complement rows. The multiple row decoder activates more than one row of the memory array at a time and the controller indicates to the multiple row decoder to activate data rows or complement rows as a function of an input pattern to be matched. The output unit indicates which columns generated a signal, the columns matching the pattern.