CAM Data Read Controller for Memory Devices

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Solution Overview

Problem

Existing memory devices face inefficiencies in cam data load operations due to the lack of effective mechanisms to stop and manage bad block information during read operations, leading to suboptimal performance and increased power consumption.

Innovation Solution

A memory device and system that includes a cam block with peripheral circuits and a cam data read controller capable of reading cam data in page units, stopping the load operation based on check data within the read cam data, thereby improving operational efficiency by selectively loading only relevant data segments.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If cam data is loaded continuously without stopping during read operations, then data transfer completeness is improved, but power consumption increases and operational efficiency decreases

Engineering Contradiction:
Improvedata transfer completenessVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The cam data read controller reads cam data in page units and monitors check data (validity indicators) within the data stream. When invalid data segments are detected through this feedback mechanism, the controller automatically stops the cam data load operation, preventing unnecessary data transfer and reducing power consumption while maintaining data integrity.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

Instead of loading all cam data continuously, the system performs partial loading by processing data in page units and stopping when validity check fails. This partial action approach loads only the necessary valid data segments, reducing overall power consumption while ensuring complete transfer of valid cam data.

Inventive Principle:
Principle #16Partial or excessive action

2Reliability

If all cam data segments are transferred regardless of validity, then data transfer completeness is improved, but processing efficiency decreases

Engineering Contradiction:
Improvedata transfer completenessVSAvoidprocessing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system extracts only the valid cam data segments from the complete data stream by monitoring check data during the read operation. When invalid segments are detected, the load operation stops, effectively taking out only the necessary valid data portions for transfer to the memory controller, thereby improving processing efficiency.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The system performs partial data transfer by loading only valid cam data segments identified through check data monitoring, rather than transferring all segments. This selective partial loading improves processing efficiency by reducing the volume of data that requires further processing in the memory controller.

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If cam data is read and loaded without selective filtering, then data completeness is improved, but decoding speed decreases

Engineering Contradiction:
Improvedata completenessVSAvoiddecoding speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The cam data read controller performs preliminary validation by reading and checking the validity of cam data segments during the read operation itself, before the data is fully loaded to the memory controller. This preliminary action of filtering invalid segments early in the process preserves data completeness for valid segments while improving decoding speed by eliminating invalid data beforehand.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11132252B2Memory device, memory system including memory device, and method of operating memory system
Publication Date: 2021.09.28 SK HYNIX INC
  • US11132252B2 patent drawing
  • US11132252B2 patent drawing
  • US11132252B2 patent drawing

AI summary

The memory device includes a content addressable memory (CAM) block including a plurality of pages, peripheral circuits configured to perform a CAM data read operation to read a CAM data comprising a plurality of check data each indicating whether bad block information is included in a region of the CAM data from a page sequentially selected among the plurality of pages, a CAM data read controller configured to perform a CAM data load operation to receive the CAM data from the peripheral circuits and output the CAM data to an external memory controller, and stop the CAM data load operation based on at least one check data among the plurality of check data included in the CAM data.