Multi-Priority CAM Encoder for Parallel Match Identification
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Solution Overview
Problem
Existing content addressable memory (CAM) systems can only record a single highest priority match, requiring manual manipulation to identify subsequent matches, which is time-consuming and inefficient when multiple matches occur.
Innovation Solution
A multi-priority encoder is developed, comprising interconnected single priority encoders that report multiple priority matches, allowing for simultaneous identification of multiple highest priority inputs by using a succession of identical logic circuits with ascending and descending priority dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single priority encoder is used to determine the highest priority match in CAM, then the encoding operation is simple and fast, but only one match can be identified requiring manual manipulation to find subsequent matches which is time-consuming
Solution Approach 1:
The priority encoder is divided into multiple independent stages, where each stage encodes a specific priority level (first priority, second priority, third priority, etc.). Each stage processes match inputs independently and produces encoded outputs for its designated priority level, allowing simultaneous identification of multiple matches without manual intervention
Solution Approach 2:
The encoder extends from a single-dimension highest-priority-only encoding to a multi-dimensional structure that encodes multiple priority levels simultaneously. By adding priority level as an additional dimension, the system can report first priority match, second priority match, and subsequent matches in parallel, transforming the output from scalar to vector
2Loss of time
If manual manipulation is used to identify subsequent matches after the highest priority match, then the encoder structure remains simple, but the process becomes time-consuming and inefficient
Solution Approach 1:
The multi-stage encoder performs preliminary encoding of all priority levels simultaneously during the same time period. Instead of sequentially identifying matches one after another, all priority encodings are prepared in advance in parallel, eliminating the time loss associated with manual re-encoding operations
3Ease of operation
If a multi-priority encoder with multiple stages is implemented, then multiple matches can be identified simultaneously improving efficiency, but the device complexity increases
Solution Approach 1:
The encoder uses identical copies of the same logic circuit structure for each priority stage. Each stage is a replica of the others, processing different priority levels with the same encoding logic. This modular copying approach simplifies design and maintenance while enabling parallel operation across multiple priority levels
Solution Approach 2:
Each priority stage is designed as a universal encoding unit that can handle any match input independently. The same logic circuit structure serves multiple functions by being replicated across different priority levels, allowing the system to automatically identify and encode multiple matches simultaneously without requiring different circuit designs for each priority level
Data Source
AI summary
A multi-priority encoder includes a plurality of interconnected, single-priority encoders arranged in descending priority order. The multi-priority encoder includes circuitry for blocking a match output by a lower level single-priority encoder if a higher level single-priority encoder outputs a match output. Match data is received from a content addressable memory, and the priority encoder includes address encoding circuitry for outputting the address locations of each highest priority match line flagged by the highest priority indicator. Each single-priority encoder includes a highest priority indicator which has a plurality of indicator segments, each indicator segment being associated with a match line input.