CAM-Based Error Injection for Memory ECC Latency Assessment
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Solution Overview
Problem
Error detection and correction techniques in processors negatively impact performance due to increased memory latency for all memory accesses, not just those with errors, making it essential to assess and improve these techniques efficiently.
Innovation Solution
An error detection and correction evaluation system that uses a cache architecture with a content addressable memory (CAM) to inject errors at specific memory locations, allowing for performance evaluation of error detection and correction techniques like SECDED and DECTED, while utilizing pre-existing logic for row repair and error injection, minimizing additional logic and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error detection and correction techniques are implemented in-line, then data reliability is improved, but memory latency increases for all memory accesses
Solution Approach 1:
The system segments error handling into two distinct paths: normal memory access path and error injection/evaluation path. The CAM (Content Addressable Memory) creates a separate evaluation mechanism that does not interfere with normal memory access latency, allowing reliability assessment without performance penalty.
Solution Approach 2:
The CAM acts as an intermediary between memory accesses and error detection logic. It stores error injection addresses and enables selective error injection without affecting the main memory access path, thus evaluating error correction techniques without increasing latency for normal operations.
2Reliability
If error detection and correction techniques are assessed using traditional methods, then reliability evaluation is achieved, but processor performance degradation is observed
Solution Approach 1:
Error addresses are pre-loaded into the CAM before evaluation begins. This preliminary action allows the error injection mechanism to operate without real-time overhead, enabling reliable error detection assessment without impacting processor performance during benchmarking.
Solution Approach 2:
The system creates a copy of the memory access path through the CAM structure, allowing error injection evaluation to occur in parallel with normal operations. This copying approach enables independent assessment of error correction techniques without degrading main processor performance.
3Adaptability or versatility
If additional logic is added for error injection and evaluation, then assessment capability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The CAM structure serves multiple functions: it acts as both a traditional content addressable memory for address matching and simultaneously as an error injection control mechanism. This multi-functionality enables error assessment capability without adding dedicated error injection hardware, thus avoiding increased device complexity and manufacturing cost.
Data Source
AI summary
A memory system includes a non-volatile memory unit, a content-addressable memory unit coupled to the non-volatile memory unit, and an error injection logic unit coupled to the non-volatile memory unit and the content addressable memory unit. The non-volatile memory unit is programmed to allow a first error injection onto a first data word using the error injection logic unit. The error injection logic in combination with the content addressable memory unit replaces a bit cell in the memory system. The memory system performs an evaluation of various error detection and correction techniques.