CAM-Based Memory Redundancy for Defect Repair
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Solution Overview
Problem
Semiconductor memory arrays often contain defective memory cells due to fabrication defects, which existing redundancy schemes struggle to efficiently address, particularly in multi-core microprocessors where cache memory arrays require effective redundancy to maintain performance.
Innovation Solution
A redundancy system utilizing a Content-Addressable Memory (CAM) array, a translation array, and a redundant data array, along with an input/output multiplexer, to identify and redirect data access from defective memory cells in a primary memory array to redundant cells, ensuring seamless operation by configuring the multiplexer with offsets for read/write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional redundancy schemes using fuse banks are used to disable defective cells, then reliability is improved, but device complexity increases due to requiring multiple fuse banks and post-fabrication processing
Solution Approach 1:
The patent extracts the redundancy control logic from separate fuse banks and integrates it into the memory array itself through programmable logic blocks. This eliminates the need for external fuse banks and post-fabrication processing, reducing device complexity while maintaining reliability
Solution Approach 2:
The memory array performs self-repair through integrated programmable logic that can automatically redirect defective cells to redundant cells during normal operation. The system serves itself by using the redundancy mechanism built into the array rather than requiring external intervention or complex control circuits
2Reliability
If dedicated redundancy resources are allocated for each memory cell, then reliability is improved, but manufacturing cost increases due to resource consumption
Solution Approach 1:
The programmable logic blocks serve multiple functions: they can be configured to redirect defective cells to different redundant locations, support various redundancy patterns (row, column, or arbitrary), and adapt to different defect configurations. This multi-functionality reduces the total number of dedicated redundancy resources needed
Solution Approach 2:
The redundancy scheme is dynamic rather than static - the programmable logic can be reconfigured after fabrication to adapt to actual defect patterns. This allows the same physical redundant cells to serve different logical positions depending on where defects are found, maximizing resource utilization
Data Source
AI summary
An apparatus for redundancy of a memory array includes a primary memory array including a plurality of memory cells, one or more of which are defective. A redundant array includes a CAM array that includes a plurality of memory cells. The CAM array is addressed by the address of a defective memory location within the primary memory array and provides a match identification and a resource identification. The redundant array also includes a translation array wherein an offset to configure an input/output multiplexer is stored. The redundant array also includes a redundant data array including a plurality of memory cells wherein one or more memory cells of the redundant data array are used instead of one or more defective memory cells of the primary array.