High Density Content Addressable Memory Multiplexing

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Solution Overview

Problem

Conventional associative memories are expensive on a per-bit basis due to the substantial area occupied by sense amplifiers, limiting their use in applications where speed and cost are concerns, especially when integrated with standard random-access memory on a common bus.

Innovation Solution

A piecewise parallel associative memory architecture that multiplexes a reduced number of sense amplifiers between sections, allowing for increased memory density at the expense of execution speed, matching the bus speed to maximize cost reduction without significantly slowing the associated computer system.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If separate sense amplifiers are provided for each memory address to enable parallel searching, then searching speed is improved, but area occupied by sense amplifiers increases substantially

Engineering Contradiction:

Improvesearching speedVSAvoidarea occupied by sense amplifiers

Core Design Contradiction:

SpeedVSArea of stationary object

Solution Approach 1:

Multiple sense amplifiers are merged into a single shared sense amplifier through the use of multiplexers. The multiplexers sequentially connect different memory address lines to the shared sense amplifier, allowing it to serve multiple addresses over time. This merging dramatically reduces the total number of sense amplifiers needed while maintaining parallel search capability across different address groups.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The system dynamically switches the connection between memory address lines and the shared sense amplifier using multiplexers controlled by address bits. This dynamic switching allows the single sense amplifier to be time-multiplexed across multiple addresses, enabling the system to adapt between serving different addresses based on the current search operation without requiring dedicated amplifiers for each address.

Inventive Principle:

Principle #15Dynamics

2Quantity of substance

If memory density is increased by reducing sense amplifier count, then cost per bit is reduced, but execution speed decreases

Engineering Contradiction:

Improvememory densityVSAvoidexecution speed

Core Design Contradiction:

Quantity of substanceVSProductivity

Solution Approach 1:

The memory address space is segmented into multiple groups, with each group assignable to different time slots in the multiplexing sequence. This segmentation allows the system to process searches for different address groups in parallel across different time periods, maintaining overall search throughput while using fewer sense amplifiers. The segmentation enables the system to achieve high memory density without proportionally sacrificing execution speed.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS9979649B2High density content addressable memory

Publication Date: 2018.05.22 WISCONSIN ALUMNI RES FOUND

AI summary

An associative memory that can be integrated with standard computer memory flexibly reduces its parallelism to match the memory bus speed thereby providing substantial increases in memory density possible by a multiplexing of sense amplifiers that otherwise dominate the memory structure. Apparent parallel operation is provided by an accumulator that reassembles the multiplex data. Higher memory density makes dual use of the associative memory as a content addressable memory and random-access memory possible.