Parallel Checker Using CAM and Zero Padding for Variable Data Widths
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Solution Overview
Problem
Conventional parallel data checkers are limited by fixed data width and test pattern length, leading to inefficiencies in power consumption and adaptability for various data communication channels.
Innovation Solution
A parallel data checker utilizing a content addressable memory (CAM) and zero padding unit to compare incoming test patterns of any length and width to expected data, generating an error count through XOR logic, allowing operation with any data word size and test pattern type.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If a parallel checker is used to reduce power consumption at high data rates, then power consumption is reduced, but the device becomes limited to a fixed data width and fixed test pattern length
Solution Approach 1:
The patent implements dynamic word width adjustment by allowing the parallel checker to operate with variable data widths (e.g., 8-bit, 16-bit, 32-bit, 64-bit words) rather than being fixed to a single width. The checker can dynamically adapt its operation to match the actual data width being tested, resolving the contradiction between using parallel architecture for power savings and maintaining adaptability to different data formats.
Solution Approach 2:
The patent changes the parameter of data word width from a fixed value to a variable parameter that can be adjusted based on the testing requirements. By implementing support for multiple word widths and allowing dynamic configuration, the system maintains the power-efficient parallel architecture while gaining versatility to handle different data formats and test pattern lengths.
2Device complexity
If a parallel checker with fixed data width is used, then the device complexity is reduced, but the adaptability to different data communication channels is limited
Solution Approach 1:
The patent implements a universal parallel checker design that can handle multiple data widths (8-bit, 16-bit, 32-bit, 64-bit) and various test pattern types (PRBS, non-PRBS, different lengths) within a single device structure. This multi-functional capability allows the checker to adapt to different data communication channels without requiring separate specialized checkers for each configuration, thus reducing overall system complexity while maintaining high adaptability.
3Adaptability or versatility
If a serial checker is used to achieve universal testing capability, then adaptability is improved, but power consumption increases significantly at high data rates
Solution Approach 1:
The patent implements a dynamic parallel checker that can adapt its word width and test pattern length to match the specific testing requirements. By dynamically configuring the parallel architecture to process data in optimized word sizes rather than bit-by-bit serialization, the system maintains universal testing capability while achieving significant power consumption reductions at high data rates compared to serial checkers.
Data Source
AI summary
Disclosed herein is a test circuit for testing a device under test (DUT). The test circuit receives a test pattern output by the DUT. A content addressable memory (CAM) stores expected test data at a plurality of address locations, receives the test pattern, and outputs an address of the CAM containing expected test data matching the received test pattern. A memory also stores the expected test data at address locations corresponding to the address locations of the CAM. A control circuit causes the memory to output the expected test data stored therein at the address output by the CAM. Comparison circuitry receives the test pattern from the input, and compares that received test pattern to the expected test data output by the control circuit, and generates an error count as a function of a number of bit mismatches between the received test pattern and the expected test data.