CAM Error Detection Using Parity and Complement Parity
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Solution Overview
Problem
As semiconductor devices shrink, the increased likelihood of soft errors due to external energy impacts, such as alpha particle bombardment, leads to bit value changes in content addressable memory (CAM), making error detection more critical, especially in detecting multiple-hit errors which were previously undetectable.
Innovation Solution
A CAM-RAM memory system design that stores both parity bits and complement parity bits in RAM, using these bits to generate an error indicator through XOR and XNOR gates, allowing for reliable detection of multiple-hit errors caused by single bit errors in the CAM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor devices are shrunk to meet consumer demand for smaller devices, then device size decreases, but the soft error rate increases due to alpha particle bombardment and other external energy impacts
Solution Approach 1:
The patent applies preliminary action by pre-storing complement parity bits in the RAM alongside regular parity bits before any error occurs. This preparatory storage of additional error detection data enables the system to detect multiple-hit errors that would otherwise be undetectable, directly addressing the increased soft error rate in shrunk devices without requiring larger device dimensions
Solution Approach 2:
The patent implements feedback by using the pre-stored complement parity bits to generate an error indicator that feeds back into the system's error detection capability. When a soft error occurs, the comparison between stored parity bits and complement parity bits provides immediate feedback about the error condition, enabling reliable detection of multiple-hit errors in the shrunk device architecture
2Quantity of substance
If only single parity bits are stored in RAM for error detection, then storage space is conserved, but multiple-hit errors caused by single bit errors in CAM remain undetectable
Solution Approach 1:
The patent applies segmentation by dividing the error detection function into two separate components: regular parity bits for single-error detection and complement parity bits for multiple-hit error detection. This segmentation allows each type of parity bit to specialize in detecting specific error patterns, thereby improving overall error detection reliability while using storage space efficiently by only adding the necessary complement parity information
Solution Approach 2:
The patent introduces complement parity bits as an intermediary element that mediates between the stored data and the error detection process. These intermediary bits serve as a reference for detecting multiple-hit errors by comparing against the regular parity bits, thereby enhancing error detection capability without requiring a complete redesign of the storage architecture
Data Source
AI summary
A method for accessing a content addressable memory (CAM) system having a CAM and random access memory (RAM) includes providing comparand data to the CAM, comparing the comparand data to entries of the CAM to determine a matching CAM entry and asserting a match signal corresponding to the matching CAM entry. In response to asserting the match signal, the method further includes providing output data, an output parity bit, and an output complement parity bit from the RAM, using the comparand data to generate a generated parity bit, and providing an error indicator based on the generated parity bit, the output parity bit, and the output complement parity bit. The error indicator may indicate an error when the generated parity bit is not equal to the output parity bit or when the output parity bit is equal to the output complement parity bit.