Area Efficient Content Addressable Memory via Shared Peripheral Circuits
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Solution Overview
Problem
Existing content addressable memory devices face inefficiencies due to numerous peripheral circuits and unsuitable column multiplexing arrangements caused by current process layout limitations, leading to increased circuit area requirements.
Innovation Solution
The proposed solution involves arranging content addressable memory circuits in a memory row with shared match lines and peripheral circuits connected through independent search bit lines, allowing for column muxing while reducing the number of components and circuit area by sharing partial components and vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If each memory column is provided with a corresponding peripheral circuit, then data access function is improved, but the number of peripheral circuits increases leading to reduced memory area efficiency
Solution Approach 1:
The patent merges peripheral circuits to serve multiple memory columns. Specifically, a first peripheral circuit serves both a first memory column and a second memory column, reducing the total number of peripheral circuits required while maintaining full data access functionality across all columns.
Solution Approach 2:
The patent implements multi-functionality in peripheral circuits where a single peripheral circuit can access multiple memory columns through column multiplexing. The peripheral circuit is designed to handle operations on different columns by receiving column select signals, making it universal rather than dedicated to a single column.
2Adaptability or versatility
If column multiplexing arrangements are implemented with current process, then layout flexibility is improved, but larger circuit area is required due to layout limitations and component location changes
Solution Approach 1:
The patent arranges memory circuits in a specific spatial configuration where memory circuits for different words are positioned adjacent to each other in the same row. This spatial arrangement enables column multiplexing by allowing shared vias and match lines to connect to multiple memory columns, achieving layout flexibility without increasing area.
Solution Approach 2:
The patent implements nesting by having multiple memory columns share common infrastructure elements such as match lines and vias. The second memory column shares a match line with the first memory column through a shared via structure, creating a nested hierarchy where smaller components are integrated within the footprint of larger structures.
Data Source
AI summary
A content addressable memory (CAM) device includes first to third CAM circuits and first to second peripheral circuits. The first CAM circuit stores a first bit of a first word. The second CAM circuit is arranged adjacent to the first CAM circuit and stores a first bit of a second word. The third CAM circuit is arranged adjacent to the second CAM circuit and store a second bit of the second word. The first to the third CAM circuits are arranged in a memory row. The first peripheral circuit accesses the first bits in the first and the second words. The second peripheral circuit accesses the second bit of the second word.