CAM Storage Schemes for Bit Error Detection
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Solution Overview
Problem
Content addressable memory (CAM) systems fail to detect matching keys due to bit errors, leading to missed record retrievals despite low error rates, necessitating improved CAM storage schemes and read operations.
Innovation Solution
The implementation of storing keys as keywords with associated parity bits and inverse keywords, along with modified word line bias settings during sense operations, allows for the detection of matching keys even when stored with bit errors, by leveraging parity bits during read operations rather than post-read error detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional CAM storage schemes are used, then storage capacity is maximized, but matching keys are missed due to bit errors
Solution Approach 1:
The key is segmented into multiple portions, with parity bits generated for each portion. This segmentation allows the system to detect and correct bit errors in individual portions without compromising the entire key matching process, thereby improving reliability while maintaining storage efficiency.
Solution Approach 2:
Parity bits are introduced as intermediary elements between the key data and the storage medium. These parity bits serve as mediators that enable error detection and correction during read operations, improving matching key detection accuracy without requiring additional redundant key copies.
2Reliability
If parity bits are added to detect bit errors, then matching key detection accuracy improves, but storage space increases
Solution Approach 1:
By segmenting the key into portions and generating parity bits for each portion rather than for the entire key, the patent minimizes the total number of parity bits required. This segmented approach improves detection accuracy for bit errors while optimizing storage space utilization.
Solution Approach 2:
The patent changes the parameter of parity bit generation from whole-key basis to portion-based basis. This parameter change reduces the overhead of parity bits while maintaining effective error detection capability, thereby improving reliability without proportionally increasing storage space requirements.
3Reliability
If multiple sense operations with modified word line bias settings are performed, then bit error detection improves, but read operation time increases
Solution Approach 1:
Parity bits are generated and stored preliminarily during the write operation, so that during read operations, the system can quickly perform sense operations using these pre-computed parity bits. This preliminary action reduces the time required for error detection during reads, as the parity information is already available without requiring complex real-time computations.
Data Source
AI summary
A memory array includes strings that are configured to store keywords and inverse keywords corresponding to keys according to content addressable memory (CAM) storages schemes. A read circuit performs a CAM read operation over a plurality of iterations to determine which of the keywords are matching keywords that match a target keyword. During the iterations, a read controller biases word lines according to a plurality of modified word line bias setting that are each modified from an initial word line bias setting corresponding to the target keyword. At the end of the CAM read operation, the read controller detects which of the keywords are matching keywords, even if the strings are storing the keywords or inverse keywords with up a certain number of bit errors.