CAM XOR-SAT Filtering with Parity-Based Match Evaluation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing hardware accelerators designed to implement k-SAT problems are unable to natively implement k-XOR-SAT clauses, requiring reformulation as k-SAT problems which increases complexity, time, hardware, and power consumption.
Innovation Solution
CAM-based circuits with auxiliary counting and logic circuits that evaluate match line voltage outputs at k discrete times to determine if a counted number of matches satisfies a pre-determined parity condition, allowing the same CAM to implement both k-XOR-SAT and k-SAT clauses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If existing hardware accelerators are used to implement k-XOR-SAT clauses, then the system can process k-SAT problems, but the complexity, time, hardware resources, and power consumption increase due to requiring reformulation as k-SAT problems
Solution Approach 1:
The patent modifies existing CAM-based hardware accelerators to perform multiple functions: they can natively implement both k-XOR-SAT clauses and k-SAT clauses without reformulation. The CAM structure is enhanced with additional logic circuits that enable it to handle XOR operations directly, making the hardware versatile for different SAT problem types while maintaining the same physical infrastructure.
Solution Approach 2:
The patent changes the operational parameters of the CAM-based accelerator by introducing new control signals and evaluation modes that enable XOR-SAT clause processing. By modifying how match lines are evaluated and how results are interpreted, the system adapts to handle k-XOR-SAT problems natively without requiring structural redesign or reformulation of the input problems.
2Adaptability or versatility
If existing hardware accelerators reformulate k-XOR-SAT as k-SAT problems, then the system can process the problems, but the processing time increases
Solution Approach 1:
The patent prepares the hardware accelerator in advance by configuring the CAM structure and auxiliary logic circuits to recognize and process XOR-SAT clause patterns directly. This preliminary configuration enables the system to handle k-XOR-SAT problems immediately upon input without requiring time-consuming reformulation steps, thus reducing processing time while maintaining problem-solving capability.
3Adaptability or versatility
If existing hardware accelerators reformulate k-XOR-SAT as k-SAT problems, then the system can process the problems, but power consumption increases
Solution Approach 1:
The patent enhances the CAM-based hardware accelerator to perform multiple functions including native k-XOR-SAT clause processing. By integrating additional logic circuits and modifying the evaluation mechanism, the system achieves versatility without proportionally increasing power consumption, as the enhancements build upon the existing energy-efficient CAM architecture rather than requiring complete redesign.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the efficient implementation of k-XOR-SAT and k-SAT-k-XOR-SAT hybrid problems with reduced time, hardware, and power consumption compared to existing accelerators, while maintaining parallel search capabilities.
Implementation Method 1
Content addressable memory ('CAM') is a type of computing memory in which stored data is searched by its content rather than its location. When a 'word' is input to a CAM, the CAM searches for the word in its contents.
Implementation Method 2
The CAM can search for the input word, by entry, along the columns of the CAM... The CAM can 'find' the input word in a given row if all the CAM cells of the given row return a match for their respective entries of the input word.
Data Source
AI summary
Examples of the presently disclosed technology provide CAM-based circuits specially constructed to implement Boolean satisfiability problems involving k-XOR-SAT clauses. With the strategic addition of auxiliary counting and logic circuits that evaluate match line voltage outputs of a CAM at k discrete times in order to determine whether a counted number of matches returned by a match line satisfies a pre-determine parity condition—where k represents a number of literals of a k-XOR-SAT clause of a Boolean satisfiability problem—a circuit of the present technology can leverage a common CAM (i.e., the same CAM) to implement the k-XOR-SAT clause and k-SAT clauses. Accordingly, this extremely versatile circuit can be used to implement k-XOR-SAT and k-SAT-k-XOR-SAT hybrid problems in less time, and with less hardware and power consumption than existing hardware accelerators.