Camera Drive Substrate Clock Phase Tuning for Temperature Bit Errors
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Solution Overview
Problem
Conventional drive substrates for high-speed cameras experience bit errors in video signals across varying temperatures, leading to increased production costs and development time due to the need for redesigning the substrate to maintain accurate clock phase shifts.
Innovation Solution
A drive substrate with a Phase-Locked Loop (PLL) circuit and phase shift control unit that adjusts the clock phase during the blanking period, detecting bit errors and repeatedly shifting the phase to prevent errors across low to high temperature ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high-speed clock is used for high-speed camera operation, then the camera can achieve high-speed performance, but bit errors occur in video signals across temperature ranges
Solution Approach 1:
The patent implements dynamic clock phase adjustment by introducing a phase shift amount register that can be updated based on temperature conditions. The system dynamically changes the clock phase shift amount in response to temperature variations, allowing the high-speed clock to maintain reliable operation across different temperature ranges without sacrificing camera speed performance.
Solution Approach 2:
The patent changes the parameter of clock phase shift amount based on temperature. By monitoring temperature and adjusting the phase shift amount accordingly, the system maintains bit error-free video signals while operating at high speeds. Different temperature ranges correspond to different optimal phase shift amounts, which are stored in lookup tables or registers.
2Ease of manufacture
If conventional drive substrate is used without temperature compensation, then production cost is reduced, but bit errors occur at low and high temperatures
Solution Approach 1:
The drive substrate performs self-diagnosis and self-adjustment by monitoring its own operating temperature and automatically adjusting the clock phase shift amount. The system includes temperature detection circuitry and phase adjustment logic that operate autonomously without requiring external intervention or complex redesign of the entire substrate, thus maintaining ease of manufacture while improving reliability.
Solution Approach 2:
The patent implements a feedback mechanism where the system monitors temperature conditions and adjusts the clock phase shift amount in response. The phase shift amount is determined based on feedback from temperature sensing, ensuring that bit errors are prevented while keeping the manufacturing process relatively simple through the use of standard feedback control components.
3Device complexity
If clock phase is fixed at room temperature setting, then simple control is achieved, but bit errors occur when temperature deviates from room temperature
Solution Approach 1:
The patent pre-calculates and stores optimal phase shift amounts for different temperature ranges in lookup tables or registers during manufacturing. When operation begins, the system simply retrieves the appropriate pre-computed phase shift amount based on the current temperature, avoiding the need for complex real-time calculations while ensuring reliable operation across temperature ranges.
Solution Approach 2:
The patent divides the temperature range into multiple segments or zones, each with its own optimal phase shift amount. By segmenting the temperature-operational space, the system can apply simple lookup-based control instead of continuous complex calculations, maintaining low device complexity while preventing bit errors across the full temperature range.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents bit errors in video signals over a wide temperature range while reducing production costs and development time by dynamically adjusting the clock phase within the blanking period.
Implementation Method 1
a PLL circuit configured to shift a phase of a clock
Data Source
AI summary
A drive substrate for a camera and a broadcast camera which are free from the occurrence of bit errors in video over a low to high temperature range while achieving reduction in a production cost and development time are provided. The phase of a clock is appropriately adjusted by repeating the processes of shifting the clock phase in a first period within a blanking period during which effective pixel data of each frame in a video signal is not used, detecting the occurrence/non-occurrence of a bit error based on the phase-shifted clock in a second period within the blanking period, and further shifting the clock phase in a third period within the blanking period.