Synchronous Camera Serial Bus Timer Synchronization
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Solution Overview
Problem
Existing camera systems connected via high-speed serial buses like USB 3.0 face complexity and reliability issues due to external synchronization signal generation and internal synchronization signal generation within cameras, leading to complicated system structures and unreliable synchronous control.
Innovation Solution
A synchronous camera system that receives packets with timer values from an external controller, uses a low-pass filter to correct internal timer values, and calculates a common timer reference value for synchronized operation, enabling reliable synchronous control across multiple cameras connected via high-speed serial buses like USB 3.0.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an external synchronization signal generator is provided separately from the camera connection structure via serial bus, then synchronous control can be achieved for each camera, but the system structure becomes complicated requiring dedicated signal lines for synchronization
Solution Approach 1:
The patent merges the synchronization signal transmission with the existing serial bus communication by embedding synchronization information within standard data packets. This eliminates the need for separate dedicated synchronization signal lines while maintaining reliable synchronous control across multiple cameras connected via the same serial bus infrastructure.
Solution Approach 2:
The serial bus is designed to serve dual purposes: transmitting both regular camera control/data packets and synchronization information simultaneously. This multi-functional use of the existing bus structure avoids adding separate synchronization hardware while ensuring reliable synchronous operation.
2Reliability
If a synchronization signal generation circuit is embedded in each camera, then synchronization between cameras can be realized, but the structure of the synchronization control circuit within the camera becomes complicated
Solution Approach 1:
The patent extracts the synchronization signal generation function from individual camera circuits and relocates it to the external controller that manages the serial bus. Each camera simply receives and follows synchronization timing information embedded in incoming packets, eliminating the need for complex internal synchronization circuitry in each camera device.
Solution Approach 2:
The controller acts as an intermediary that generates and distributes synchronization timing information to all cameras through the serial bus. This centralized approach simplifies individual camera designs while maintaining reliable synchronization across the entire system through the mediating controller.
3Device complexity
If packet arrival time fluctuation is not compensated for in high-speed serial bus interfaces like USB 3.0, then the system structure remains simple, but a certain level of reliability cannot be ensured for synchronous control
Solution Approach 1:
The patent implements a feedback mechanism where each camera monitors the arrival timing of packets relative to its internal clock and reports timing deviations back to the controller. The controller uses this feedback information to adjust future packet transmission timing, compensating for bus fluctuation and ensuring reliable synchronous control while maintaining relatively simple system architecture.
Solution Approach 2:
The system dynamically adjusts packet transmission parameters (timing, intervals) based on observed bus fluctuation patterns. By changing these parameters adaptively, the system compensates for timing variations in high-speed serial bus interfaces like USB 3.0, maintaining synchronization reliability without requiring complex additional hardware.
Data Source
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AI summary
A low-pass filter operation circuit 113 constitutes a serial interface circuit, which enables communication conforming to the serial bus standard including IEEE 1394 and USB 3.0, together with a timer register 114, a packet receiving circuit 111, and a packet transmitting circuit 112. Further, the low-pass filter operation circuit 113 performs a correction process of gradually increasing or decreasing an internal timer value counted by the timer register 114 by a unit count value of the timer register 114, thereby converging the deviation. A timer operation circuit 15 calculates a timer reference value, corresponding to the timing at which synchronization is to be carried out next, common to cameras 1, ..., 1, on the basis of a timer value maintained in the timer register 114, and a frame rate generated by a CPU 14.