CAMM LPDDR Memory Module Vertical Stacking
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Solution Overview
Problem
Existing Information Handling Systems (IHSs) face challenges in efficiently processing and storing data due to congestion and power consumption issues with conventional Double Data Rate (DDR) memory modules, particularly in small form factor devices, which restricts further size reduction and increases motherboard complexity.
Innovation Solution
The implementation of a Compression Attached Memory Module (CAMM) using Low-Power Double Data Rate (LPDDR) memory modules, where LPDDR devices are attached to a cDIMM connector via mechanical compression, allowing for modular deployment and reduced motherboard footprint, with surface contact connections optimizing trace routing and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If conventional DDR memory modules are used, then memory capacity can be maintained, but power consumption increases and motherboard footprint increases
Solution Approach 1:
The patent transitions from conventional DDR memory to LPDDR (Low Power DDR) memory, changing the operational parameters of the memory system to achieve lower power consumption while maintaining compatibility with existing memory interfaces and architectures
Solution Approach 2:
The patent introduces a vertical stacking architecture where memory devices are stacked above the cDIMM connector in the Z-dimension, allowing the memory module to have a smaller horizontal footprint on the motherboard while maintaining or increasing total memory capacity through vertical expansion
2Volume of moving object
If memory module size is reduced for small form factor devices, then device compactness improves, but motherboard complexity increases
Solution Approach 1:
The patent segments the memory system into modular components: LPDDR memory devices, a cDIMM connector, and surface contact connections. This modular segmentation allows for compact integration while simplifying motherboard design through standardized interfaces and reduced routing complexity
Solution Approach 2:
By moving memory contacts to the surface of the memory module and using vertical stacking, the patent reduces the horizontal space required on the motherboard, thereby reducing overall device footprint without increasing motherboard complexity
3Adaptability or versatility
If surface contact connections are used, then trace routing flexibility increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent introduces surface contact connections as an intermediary between the memory module and the cDIMM connector. These surface contacts provide flexible trace routing capabilities while incorporating alignment features that maintain manufacturing feasibility through standardized mechanical interfaces
4Quantity of substance
If LPDDR devices are stacked vertically, then memory capacity increases without increasing footprint, but mechanical compression requirements increase
Solution Approach 1:
The patent implements a vertical stacking architecture where LPDDR memory devices are stacked above the cDIMM connector, with each layer nested vertically. This allows multiple memory devices to be integrated in a compact volume, increasing total memory capacity without increasing the horizontal footprint
Solution Approach 2:
The patent combines multiple LPDDR memory devices into a single stacked assembly that interfaces with the cDIMM connector through surface contacts. This merging of multiple memory devices into one modular unit achieves higher capacity while managing mechanical compression through the unified structure
Data Source
AI summary
Embodiments of systems and methods for a Compression Attached Memory Module (CAMM) for Low-Power Double Data Rate (LPDDR) memories are described. In an illustrative, non-limiting embodiment, an Information Handling System (IHS) may include: a compression Dual In-Line Memory Module (cDIMM) connector coupled to a motherboard; and a memory module coupled to the cDIMM connector, where the memory module comprises an LPDDR device coupled to a top surface of the memory module and accessible via surface contact connections disposed on a bottom surface of the memory module.