Microcontroller CAN Module Buffer Descriptor Table Optimization
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Solution Overview
Problem
Current CAN controller architectures require significant silicon area and processing power due to the need for multiple receive buffers and filters, which can lead to message loss when overwhelmed by traffic, especially with slower processors.
Innovation Solution
A lightweight buffer descriptor table (BDT) is implemented in a microcontroller, allowing for efficient storage of CAN messages with constant-sized entries that include message identifiers and data, reducing the need for dedicated buffers and minimizing silicon real estate by merging status fields and eliminating pointer overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple receive buffers and filters are implemented in CAN controller architecture, then message reception capability is improved, but silicon area and processing power requirements increase
Solution Approach 1:
The patent merges multiple receive buffers into a single buffer and combines multiple filters into a single filter. The controller architecture integrates the filter and buffer resources, allowing one filter to service multiple message buffers. This consolidation reduces the silicon area required while maintaining the capability to handle multiple message streams through software-managed buffer descriptors.
Solution Approach 2:
The single filter is designed to be universal, capable of filtering messages for multiple different buffers. The filter descriptor table allows the same filter hardware resource to be dynamically assigned to different buffer descriptors, enabling one filter to perform the work of multiple dedicated filters. This multi-functionality reduces overall silicon area while preserving message reception capability.
2Reliability
If multiple receive buffers and filters are implemented in CAN controller architecture, then message reception capability is improved, but processing power requirements increase
Solution Approach 1:
The controller architecture implements self-service through automatic filter matching and buffer descriptor management. When a message is received, the filter automatically matches it against the appropriate buffer descriptor without requiring CPU intervention for each message. The system manages its own buffer assignments and filter matching, reducing the processing burden on the main CPU and overall system power consumption.
Solution Approach 2:
The patent extracts the complex buffer management logic from the CPU and implements it in the controller's dedicated descriptor table structure. The buffer descriptors contain pre-configured filtering criteria and buffer assignments, allowing the controller to handle message routing independently. This extraction of management functions from the CPU reduces processing power requirements while maintaining comprehensive message reception capability.
3Reliability
If dedicated buffers are used for each message stream, then message storage reliability is improved, but silicon real estate increases
Solution Approach 1:
The patent implements dynamic buffer assignment where buffer descriptors can be dynamically allocated and reassigned based on message traffic patterns. Instead of static dedicated buffers, the system uses a descriptor table that allows flexible assignment of buffer resources to different message streams as needed. This dynamic approach maintains reliable message storage for active streams while freeing silicon real estate by releasing buffers from idle streams.
Solution Approach 2:
The system changes the parameter of buffer allocation from fixed/dedicated to variable/sharable. By using buffer descriptors that can be dynamically assigned to different message streams, the same physical buffer resources serve multiple logical message streams. This parameter change allows the system to maintain reliable storage for prioritized messages while reducing total silicon real estate requirements through resource sharing.
Data Source
AI summary
A microcontroller has a random access memory, and a Controller Area Network (CAN) controller with a control unit receiving an assembled CAN message. The control unit generates a buffer descriptor table entry using the assembled CAN message and stores the buffer descriptor table entry in the random access memory, and the buffer descriptor table entry has at least a message identifier and load data from the CAN message and information of a following buffer descriptor table entry.