Bit-Timing Symmetrization for CAN Bus Oscillator Tolerance
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Solution Overview
Problem
Conventional CAN bus systems face performance limitations due to asymmetrical bit timing, which narrows the synchronization margin, affects oscillator tolerance, and restricts baud rate, leading to EMC issues and the need for increased driver speed.
Innovation Solution
A bus system with a bit timing symmetrization component that delays recessive to dominant edges and adjusts bit transmission timing to achieve symmetrical bit streams, integrated within the bus controller, allowing for configurable delays and improved signal reception and transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the sample point is shifted towards the end of the bit time to catch the delayed recessive value, then the bit timing can accommodate the slow bus transition, but the synchronization margin is narrowed and oscillator tolerance decreases
Solution Approach 1:
The patent applies asymmetry by introducing different delay amounts for dominant and recessive bits. Recessive bits receive a first delay amount while dominant bits receive a second delay amount, creating asymmetric timing compensation that counteracts the inherent bus asymmetry. This allows the sample point to remain at an optimal position while still accommodating the slow bus transition characteristics.
Solution Approach 2:
The patent changes the timing parameters by introducing configurable delay amounts that can be adjusted based on the specific bus characteristics. The delay amounts are determined based on the measured bus transition characteristics, allowing the system to adapt to different bus conditions and maintain optimal synchronization margin while compensating for timing delays.
2Productivity
If the CAN baud rate is increased to improve system performance, then the communication speed improves, but the oscillator tolerance decreases and EMC issues worsen
Solution Approach 1:
The patent applies preliminary action by pre-compensating for bit timing delays through the introduction of delay circuits that add configurable delay amounts to dominant and recessive bits before they are transmitted. This preliminary timing adjustment ensures that bits are sampled at the correct time even at higher baud rates, maintaining oscillator tolerance while enabling improved communication speed.
3Speed
If the CAN driver speed is increased to improve communication performance, then the baud rate increases, but the EMC behavior deteriorates
Solution Approach 1:
The patent changes the timing parameters by introducing configurable delay amounts that compensate for bus transition characteristics. This allows the system to use slower driver speeds with better EMC behavior while maintaining effective communication performance through the timing compensation mechanism. The delay circuits adjust the bit timing to account for the slower transitions, eliminating the need for high-speed drivers.
Data Source
AI summary
A bus interface, for allowing a plurality of devices to communicate with one another via the bus, includes a bit timing symmetrization component for symmetrizing the bit stream. For an incoming bit stream, the bit timing symmetrization component further includes an input delay filter for delaying recessive to dominant edges for a given received bit stream and sampling the delayed input signal at the sample point. In one embodiment, bit timing synchronization may still be performed with the undelayed recessive to dominant edges. For an outgoing bit stream, the bit timing symmetrization component transmits a recessive bit, that followed a previously transmitted dominant bit, before the start of the next bit time, and transmits a dominant bit, that followed a previously transmitted recessive bit, with a delay of a configurable amount of time.