CAN Bus User Station Bit Rate Switching Synchronization
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Solution Overview
Problem
The existing CAN bus system faces challenges in maintaining clock tolerance and robustness when switching between different bit rates, particularly at high bit rate ratios, which can lead to synchronization issues and increased demands on clock accuracy.
Innovation Solution
A user station with a communication control unit that includes predetermined bit patterns for bit rate switching, allowing for synchronization before and after the switching time, and enabling robust synchronization and mode switching, even at high bit rate ratios, by using fixed bit patterns to ensure exclusive access to the bus and handle reception errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If switching to a higher bit rate within a message is implemented to increase data transmission rate, then the useful data length is increased and data transmission rates are significantly higher, but the demand on clock tolerance increases drastically
Solution Approach 1:
The patent applies preliminary action by performing a hard synchronization at the end of the FDF bit before the bit rate switching occurs. This pre-synchronization ensures that all bus users are properly aligned before transitioning to the higher bit rate, thereby maintaining clock tolerance despite the increased transmission rate. The synchronization jump width is configured to compensate for expected phase errors accumulated during the arbitration phase, preventing synchronization issues in the data phase.
2Reliability
If the bit time is made significantly longer than twice the signal propagation time to allow for arbitration and acknowledgment, then synchronization is maintained, but the data transmission rate is restricted
Solution Approach 1:
The patent segments the message transmission into two distinct phases with different bit rates: an arbitration phase transmitted at a lower bit rate (1 Mbit/s) and a data phase transmitted at a higher bit rate (up to 12 Mbit/s). This segmentation allows the system to maintain reliable synchronization during arbitration while achieving high-speed data transmission during the data phase, effectively resolving the contradiction between synchronization reliability and transmission speed.
Solution Approach 2:
The patent implements dynamic bit rate switching within a single message frame. The system transitions from a static low bit rate for the entire message to a dynamic approach where the bit rate changes based on the phase of transmission. This dynamic switching enables the system to adapt the transmission rate to the specific requirements of each phase, achieving both reliable arbitration and high-speed data transfer.
3Reliability
If the synchronization jump width is increased to compensate for phase errors at high bit rate ratios, then clock tolerance is improved, but the synchronization precision during switching is reduced
Solution Approach 1:
The patent applies local quality by configuring different synchronization jump widths for different phases of message transmission. A larger synchronization jump width is used during the arbitration phase to accommodate the lower bit rate and longer bit times, while a smaller synchronization jump width is used during the data phase at higher bit rates. This localized optimization of synchronization parameters maintains both clock tolerance and synchronization precision in their respective phases.
Data Source
AI summary
A user station for a bus system and a method for transmitting a message at different bit rates in a bus system. The user station includes a communication control unit for creating a message for a further user station of the bus system. The communication control unit provides, in the message, a first phase, which is to be transmitted at a first bit rate, and to provide a second phase, which is to be transmitted at a second bit rate, which is faster than the first bit rate. The communication control unit is designed to provide in the message a first predetermined bit pattern for a bit rate switching between the first and second bit rate and to provide a second predetermined bit pattern for a bit rate switching between the second and first bit rate. The second predetermined pattern differs from all other bit patterns in a valid message.