CAN Bus Interface Circuit for Stable Dominant-Recessive Transitions
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Solution Overview
Problem
Existing devices connected to CAN FD SIC buses experience parasitic oscillations and impedance issues during dominant to recessive bit transitions, failing to comply with signal cancellation restrictions.
Innovation Solution
A device with specific transistor and diode configurations, controlled by a circuit to maintain transistors in an ON state during defined time periods, ensuring consistent impedance and absorbing common mode overvoltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional emitting/receiving devices are connected to CAN FD SIC bus, then basic communication function is achieved, but parasitic oscillations occur and impedance restrictions are not complied
Solution Approach 1:
The control circuit activates the PMOS and NMOS transistors in advance during the recessive bit transmission phase, before the dominant bit is transmitted. This preliminary action ensures that the impedance is already optimized and the transistors are ready to handle the upcoming signal transition, preventing parasitic oscillations from occurring during the critical dominant to recessive bit transition.
Solution Approach 2:
The patent employs dynamic control of transistor states based on the communication protocol requirements. The control circuit adjusts the ON/OFF state of PMOS and NMOS transistors according to the current bit transmission phase (dominant or recessive), allowing the device to adapt its impedance characteristics dynamically during communication to comply with CAN FD SIC restrictions and eliminate parasitic oscillations.
2Object-affected harmful factors
If transistors are controlled to maintain specific impedance during bit transitions, then parasitic oscillations are reduced, but device complexity increases
Solution Approach 1:
The patent combines multiple functions into a single integrated circuit structure. The PMOS and NMOS transistors are merged with pull-up and pull-down resistors in a coordinated arrangement, where the control circuit simultaneously manages the states of multiple components to achieve impedance optimization. This merging reduces the need for separate impedance matching circuits and simplifies the overall device architecture.
Solution Approach 2:
The control circuit serves multiple functions: it manages the ON/OFF states of PMOS and NMOS transistors, optimizes impedance during bit transitions, and ensures compliance with CAN FD SIC restrictions. By making the control circuit multi-functional, the patent avoids adding separate dedicated circuits for each function, thereby reducing overall device complexity while achieving the desired oscillation reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces parasitic oscillations and maintains desired impedance, complying with CAN FD SIC restrictions by stabilizing signal transitions and absorbing overvoltages.
Implementation Method 1
absorbing common mode overvoltages
Data Source
AI summary
The present disclosure relates to device including first and second terminals connected to a bus, third and fourth terminals connected to power supply and reference potentials. A first transistor and a first resistor are in series between the first terminal and a first diode connected to the third terminal. A second resistor, a second transistor and a second diode are in series between the first and fourth terminals. A third transistor and a third resistor are in series between the first diode and the second terminal. A fourth resistor, a fourth transistor and a third diode are in series between the second and fourth terminals. At each consecutive transmission of a dominant bit and of a recessive bit, a circuit sets the transistors at the ON state during a time period starting with the recessive bit.