CAN Device Identifier Comparison for Malicious Message Invalidation
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Solution Overview
Problem
In-vehicle networks using the CAN bus protocol face significant security concerns, including intrusion detection and prevention, as compromised networks can allow attackers to maliciously control vehicle components, with existing solutions insufficient to effectively address these issues.
Innovation Solution
A Controller Area Network (CAN) device is configured with a compare module that interfaces with a CAN transceiver, featuring a receive data input interface, a CAN decoder, an identifier memory, compare logic, and a signal generator. The device decodes CAN message identifiers, compares them to stored entries, and outputs a match signal to invalidate malicious messages by generating dominant bits following the FDF field, preventing message transmission until an ACK slot or a threshold bit rate is reached.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a CAN device monitors and compares identifiers to detect malicious messages, then network security is improved, but device complexity increases due to additional compare module components
Solution Approach 1:
The compare module is integrated within the CAN device, merging the security monitoring functionality with the existing CAN protocol handling components. This consolidation improves network security by enabling real-time identifier comparison and malicious message detection while avoiding the overhead of completely separate security hardware.
Solution Approach 2:
The identifier memory pre-stores valid identifier entries before communication occurs, enabling the compare logic to immediately recognize and filter malicious messages without requiring complex real-time analysis. This preliminary preparation of reference data simplifies the detection process while maintaining high security standards.
2Reliability
If the device invalidates malicious CAN messages by generating dominant bits, then network security is improved, but message transmission speed is reduced due to additional validation processing
Solution Approach 1:
The compare logic performs rapid identifier comparison operations that complete before full message transmission, allowing the system to quickly identify and invalidate malicious messages. This fast comparison mechanism rushes through the validation process efficiently, minimizing the impact on overall transmission speed while maintaining security.
Solution Approach 2:
The compare module acts as an intermediary between the CAN transceiver and the network, intercepting and validating messages before they fully propagate. This intermediate validation layer efficiently filters malicious content while allowing legitimate messages to pass through with minimal delay, balancing security and speed.
3Measurement precision
If the compare module stores multiple identifier entries in memory, then detection capability is improved, but memory usage increases
Solution Approach 1:
The identifier memory stores a selective subset of identifier entries that are most relevant for detecting malicious messages in the specific network context. Rather than storing all possible identifiers, the system uses partial action by storing only the necessary reference entries, achieving effective detection capability while optimizing memory usage.
Data Source
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AI summary
A Controller Area Network, CAN, device comprising: a compare module configured to interface with a CAN transceiver, a CAN decoder configured to decode an identifier of a CAN message received from the RXD input interface; an identifier memory configured to store an entry that corresponds to at least one identifier; compare logic configured to compare a received identifier from a CAN message to the entry that is stored in the identifier memory and to output a match signal upon a match; a signal generator configured to output, in response to the match signal, a signal to invalidate the CAN message, wherein the signal is output from the TXD output interface to the CAN transceiver; and wherein the signal generated by the signal generator provides for one or more dominant bits that are timed so that at a bit immediately following a FDF field or the FDF field bit is made dominant.