Master-Slave CAN FD Bus for Collision-Free Vehicle LED Networks
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Solution Overview
Problem
Existing high data rate vehicle communication systems, such as those for sophisticated LED lighting systems, face challenges in achieving cost-effectiveness, robustness, and safety while relying on complex and expensive protocol controllers and accurate clock sources, which increase production costs in the automotive industry.
Innovation Solution
A master-slave communication bus interface using the CAN FD protocol with differential bus wiring and cyclic redundancy check (CRC) for error detection, allowing slaves to send data only upon request and using a regular data stream as a 'heartbeat' to prevent collisions and ensure safety, thus reducing complexity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex and accurate protocol controllers using external components are used to achieve high data rate communication, then communication reliability and data rate are improved, but production cost increases
Solution Approach 1:
The patent combines the protocol controller functionality directly into the transceiver chip, eliminating the need for separate external protocol controllers. This integration reduces the number of components, simplifies the system architecture, and lowers production costs while maintaining high data rate communication reliability through the unified design of the transceiver and protocol handling capabilities.
Solution Approach 2:
The transceiver chip is designed to perform multiple functions including signal transmission, reception, and protocol control within a single device. This multi-functional approach eliminates the need for dedicated external protocol controllers and reduces overall system complexity while maintaining communication reliability.
2Ease of manufacture
If single-chip technologies such as BCD technology are used for LED drivers, then cost efficiency is improved, but dependence on accurate clock source (crystal) increases
Solution Approach 1:
The patent extracts the clock source functionality from external crystal oscillators and integrates it directly into the transceiver chip. This integration reduces dependence on external accurate clock sources while maintaining timing precision for high data rate communication, and simplifies the bill of materials by eliminating separate crystal components.
Solution Approach 2:
The transceiver chip generates its own clock signals internally through integrated oscillators, making it self-sufficient and reducing dependence on external crystal sources. This self-service approach maintains cost efficiency with single-chip BCD technology while ensuring reliable timing without external components.
3Reliability
If differential wiring is adopted for clock and data signals to facilitate robustness, then communication robustness is improved, but wire harness cost increases
Solution Approach 1:
The patent combines clock and data signals into a single communication channel using CAN FD protocol, eliminating the need for separate differential wiring for clock signals. This integration reduces wire harness complexity and cost while maintaining robustness through the differential signaling already inherent in CAN bus architecture.
Solution Approach 2:
The communication bus is designed to carry both clock synchronization and data transmission functions through a single differential pair, eliminating the need for separate dedicated clock wiring. This multi-functional approach reduces wire harness complexity while maintaining communication robustness.
Data Source
AI summary
A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.