CAN Node Security Module Using 10-Bit Error Flags
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Solution Overview
Problem
In-vehicle networks using the CAN bus protocol face significant security concerns, including intrusion detection and prevention, as malicious actors can compromise the network by sending spoofed messages with matching identifiers, potentially leading to control of vehicle components.
Innovation Solution
A security module for CAN nodes that receives data from the CAN bus, compares frame identifiers with local identifiers, and outputs an error signal by setting a predetermined number of consecutive dominant bits to a dominant value, distinguishing security errors from form errors and alerting other nodes to network attacks while invalidating malicious messages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the CAN bus uses standard error flags with 6 consecutive dominant bits as defined by ISO 11898-1, then form errors can be detected, but security errors cannot be distinguished from form errors
Solution Approach 1:
The patent segments the error detection mechanism by creating a separate security error flag with a distinct bit pattern (10 consecutive dominant bits) from the standard form error flag (6 consecutive dominant bits). This segmentation allows the system to differentiate between security errors and form errors, resolving the contradiction by maintaining both error detection capabilities simultaneously.
Solution Approach 2:
The patent changes the parameter of consecutive dominant bits from 6 bits (standard form error) to 10 bits (security error). This parameter change enables the system to distinguish security errors from form errors while maintaining compatibility with the existing CAN bus protocol, thus improving security error detection without losing error type differentiation.
2Reliability
If the security module sets a predetermined plurality of consecutive bits to dominant value to indicate security error, then security errors are uniquely identified, but the error signal may conflict with standard CAN error flags
Solution Approach 1:
The patent resolves the potential conflict by changing the parameter of consecutive dominant bits to 10 bits for security errors, which is longer than the standard 6-bit form error flag. This parameter differentiation ensures that security error flags and form error flags are distinguishable, maintaining reliability while managing device complexity through clear parameter distinction.
3Reliability
If the CAN network implements intrusion detection by comparing identifiers, then malicious messages can be detected, but legitimate message transmission may be delayed due to security checks
Solution Approach 1:
The patent implements preliminary action by pre-configuring the security module with the predetermined plurality of consecutive bits (10 dominant bits) that will be set to indicate a security error. This preliminary setup allows the module to quickly detect and respond to intrusions by immediately setting the distinctive bit pattern when a security error is detected, minimizing transmission delay while maintaining reliable intrusion detection.
Data Source
AI summary
A security module (460) for a CAN node (402). The security module (460) comprises: a RXD input interface for receiving data from a CAN bus (404), and a TXD output interface for transmitting data to the CAN bus (404). The security module (460) is configured to: receive a CAN frame from the CAN bus via the RXD input interface; compare an identifier of the received CAN frame with at least one identifier associated with a local controller (410); and upon detection of a match between the identifier of the received CAN frame and the at least one identifier associated with the local controller (410), output an error signal to the CAN bus via the TXD output interface by setting a predetermined plurality of consecutive bits (682) in the CAN frame to a dominant value. The predetermined plurality of consecutive bits (682) identifies a security error to CAN nodes connected to the CAN bus (404) and is at least 10 consecutive bits.