CAN Transceiver Voltage Control for Reflection-Free Bus Switching
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Solution Overview
Problem
CAN transceivers experience signal reflection and oscillation during transitions between dominant and recessive frames, leading to increased bit error rates and reduced transmission reliability and efficiency.
Innovation Solution
A CAN transceiver design that controls the voltage difference between high-side and low-side signals within specific threshold ranges based on the mode control signal and data transmission level, using transistors and switches to manage impedance and prevent signal oscillation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the transmission rate of the CAN bus is reduced to avoid erroneous outputs, then the reliability of data reception is improved, but the signal transmission efficiency deteriorates
Solution Approach 1:
The patent changes the voltage difference parameter between high-side and low-side signals during transitions. Specifically, it controls the voltage difference to be within 1.8V to 3.3V during dominant frames and within -1.8V to -3.3V during recessive frames, preventing oscillation and erroneous outputs while maintaining high transmission rates without reducing the CAN bus transmission rate
Solution Approach 2:
The patent dynamically adjusts the output resistance of the CAN controller during frame transitions. By making the output resistance adjustable rather than fixed, the system can optimize performance for different frame types (dominant/recessive) and transmission conditions, maintaining both high reliability and transmission efficiency
2Productivity
If the output resistance of the CAN controller changes suddenly during signal transitions, then the data transmission capability is improved, but signal oscillation and reflection occur causing erroneous outputs
Solution Approach 1:
The patent applies preliminary anti-action by pre-controlling the voltage difference between high-side and low-side signals before complete transitions occur. The controlled voltage difference prevents oscillation and reflection from occurring in the first place, rather than attempting to correct them after they occur, thereby maintaining both transmission capability and signal stability
Solution Approach 2:
The patent performs preliminary action by establishing the appropriate voltage difference range before the transition completes. The system prepares the signal levels in advance to ensure smooth transitions between dominant and recessive frames, preventing erroneous outputs while maintaining high data transmission capability
Data Source
AI summary
A CAN transceiver having a data transmission port, control port, high-side bus port and low-side bus port. When the mode control signal is in a first state and data transmission signal is at logic low level, the voltage difference between the high-side signal and low-side signal is between 1.8 V and 3.3 V; when the mode control signal is in the first state and data transmission signal is at logic high level, the voltage difference between the two is between −1.8 V to −3.3 V; when the mode control signal is in a second state and data transmission signal is at logic low level, the voltage difference between the two is between 1.8 V to 3.3 V; when the mode control signal is in the second state and data transmission signal is at logic high level, the voltage difference between the two is between −300 mV and 300 mV.