CAN Transceiver Circuit for Fast Bus Capacitance Reduction
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Solution Overview
Problem
The presence of parasitic capacitance due to DEPMOS transistors in CAN devices during arbitration loss affects signal integrity on the CAN bus, as existing methods to turn off DEPMOS transistors are not rapid enough to mitigate capacitive loading during transmission.
Innovation Solution
An arbitration detection circuit is implemented to quickly determine arbitration loss, enabling the disabling of DEPMOS transistors to reduce parasitic capacitance by controlling the gate voltage and using error mitigation circuits to prevent false detections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If existing methods are used to turn off DEPMOS transistors during arbitration loss, then the transistors are eventually disabled, but the turning-off process is not rapid enough to mitigate capacitive loading during transmission
Solution Approach 1:
The patent applies preliminary action by pre-charging the gate voltage of the DEPMOS transistor through a pull-up circuit before arbitration loss occurs. When arbitration loss is detected, the transistor is already in a state ready for rapid turn-off, eliminating the delay associated with gradual voltage discharge and enabling immediate capacitance reduction.
Solution Approach 2:
The patent implements dynamics by using a dynamic control mechanism that rapidly switches the DEPMOS transistor between on and off states based on arbitration status. The gate voltage is dynamically adjusted from a pre-charged high state to a low state through controlled discharge, enabling the transistor to respond quickly to arbitration loss conditions rather than following a fixed timing sequence.
2Reliability
If DEPMOS transistors are disabled rapidly to reduce parasitic capacitance, then signal integrity is improved, but the complexity of the control circuit increases
Solution Approach 1:
The patent applies feedback by implementing an arbitration detection circuit that continuously monitors the arbitration status and provides real-time feedback to the DEPMOS control circuit. When arbitration loss is detected, the feedback signal triggers immediate gate voltage discharge, creating a closed-loop control system that automatically responds to bus conditions without requiring complex external control logic.
Solution Approach 2:
The patent implements self-service by designing a control circuit that autonomously manages the DEPMOS transistor state based on detected arbitration conditions. The circuit automatically detects arbitration loss, activates the discharge path, and restores the transistor to the off state without requiring external intervention, thereby improving signal integrity while maintaining manageable circuit complexity through self-contained functionality.
3Object-affected harmful factors
If the gate voltage of DEPMOS transistor is discharged through a resistor, then the transistor turns off, but the process is too slow to mitigate capacitive loading during transmission
Solution Approach 1:
The patent applies preliminary action by pre-charging the gate voltage to a high state before arbitration loss occurs. This creates a large voltage differential that drives rapid discharge current through the resistor when arbitration loss is detected, significantly accelerating the turn-off process compared to gradual voltage reduction methods and enabling timely capacitance reduction.
Solution Approach 2:
The patent implements periodic action by using a controlled discharge mechanism that activates only when arbitration loss is detected. The discharge path is periodically enabled based on arbitration status, creating a pulsed high-current discharge event that rapidly reduces capacitance only when needed, rather than continuously discharging which would be time-consuming and unnecessary during normal operation.
Data Source
AI summary
In some examples, a circuit includes a first transistor, a second transistor, a first resistor, and a digital logic circuit. The first transistor has a control terminal and first and second terminals. The second transistor has a control terminal and first and second terminals, the first terminal of the second transistor coupled to the second terminal of the first transistor. The first resistor has first and second terminals, the first terminal of the first resistor coupled to the control terminal of the second transistor, and the second terminal of the first resistor coupled to the first terminal of the second transistor. The digital logic circuit has an output terminal and first and second input terminals, the output terminal of the digital logic circuit coupled to the control terminal of the second transistor, the first input terminal of the digital logic circuit coupled to a data transmit input terminal of the circuit, and the second input terminal of the digital logic circuit coupled to a data receive output terminal of the circuit.