CAN Transceiver Adjustable Delay Circuits for EMC and Bit Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing CAN transceivers face challenges in adapting to increasing data rates and evolving standards, as bit timing and wave-shaping parameters are not independently adjustable, leading to difficulties in meeting electromagnetic compatibility and bit timing requirements.
Innovation Solution
The introduction of adjustable delay circuits within the CAN transceiver allows for independent trimming of bit timing parameters Tbit(bus), Tbit(rxd), and dTrec, enabling optimization of wave-shaping and bit timing to meet changing specifications, both at the manufacturer and in the field.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If wave-shaping is applied to meet EMC requirements, then electromagnetic compatibility is improved, but bit timing parameters deteriorate due to slowed Vdiff transitions
Solution Approach 1:
The patent segments the control of bit timing parameters into four independent delay circuits (Td1, Td2, Td3, Td4) that can be individually adjusted. This segmentation allows wave-shaping delays to be separated from bit timing parameter control, enabling independent optimization of both EMC compliance and bit timing precision without mutual interference.
Solution Approach 2:
The patent introduces dynamically adjustable delay circuits that can be trimmed to different values. These delay circuits provide dynamic control over bit timing parameters (Tbit(bus), Tbit(rxd), dTrec) allowing the system to adapt to different data rates and standards while maintaining both wave-shaping requirements and precise bit timing.
2Ease of manufacture
If fixed design methodology is used, then manufacturing simplicity is improved, but adaptability to changing standards and future data rates deteriorates
Solution Approach 1:
The patent implements dynamic adjustability through trimmable delay circuits that can be configured for different bit timing parameters. This allows a single fixed hardware design to adapt to current and future CAN standards and data rates by simply adjusting the delay circuit values, maintaining manufacturing simplicity while achieving high adaptability.
Solution Approach 2:
The patent enables parameter changes by providing independent control over Td1, Td2, Td3, and Td4 delays. This allows the bit timing parameters (Tbit(bus), Tbit(rxd), dTrec) to be adjusted to match different CAN standards and future data rate requirements without changing the fundamental hardware architecture.
3Manufacturing precision
If existing transceiver designs are used, then current bit timing requirements are met, but independence in adjusting Tbit(bus), Tbit(rxd), and dTrec is lost
Solution Approach 1:
The patent divides the bit timing control into four separate, independently adjustable delay circuits (Td1 for rising edge transmit, Td2 for falling edge transmit, Td3 for rising edge receive, Td4 for falling edge receive). This segmentation enables independent adjustment of Tbit(bus), Tbit(rxd), and dTrec parameters while maintaining precise bit timing control.
Solution Approach 2:
The patent provides dynamic independence in parameter adjustment through trimmable delay circuits that can be individually configured. Each delay circuit (Td1-Td4) can be adjusted independently to achieve the desired combination of Tbit(bus), Tbit(rxd), and dTrec parameters, giving full control over bit timing characteristics.
Data Source
Figure 1
Figure 2~3
Figure 4~5
AI summary
A CAN transceiver (1) includes a first terminal which receives a transmit signal (CANTXD) from a CAN microcontroller (3). A splitter unit (4) transmits a signal derived from the transmit signal (CANTXD) to a CAN bus (2) a via bus connection. A unit receives signals from the CAN bus (2) via the bus connection. A second terminal sends a receive signal (CANRXD) derived from the received signals to the CAN microcontroller (3). The transmit and receive signals (CANTXD,CANRXD) include a pulsed signal waveform which represents data bits. Delay circuits apply a deliberate delay to the rising or falling edge of pulses of the transmit signal (CANTXD) and/or a deliberate delay to the rising or falling edge of pulses of the receive signal (CANRXD).