CAN Transceiver SiC Circuit for Differential Output Ringing

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Solution Overview

Problem

Ringing and data corruption occur in CAN transceivers due to capacitive and inductive loads during transitions between dominant and recessive states, especially at higher data rates, leading to electromagnetic interference and incorrect bit value readings.

Innovation Solution

A transceiver with a signal improvement capability (SiC) circuit that includes switches and drivers controlled by control circuitry to manage transient signals, dissipating ringing and improving data integrity by collapsing differential voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data rate is increased in CAN transceiver, then communication speed is improved, but ringing and electromagnetic interference increase causing data corruption

Engineering Contradiction:
Improvedata rateVSAvoiddata integrity
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The SiC circuit is activated before state transitions occur in the CAN transceiver. By preemptively enabling the switching elements and drivers in the SiC circuit, transient signals are managed before they can cause ringing, thus maintaining data integrity at higher data rates without adding latency to the communication protocol

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The SiC circuit acts as an intermediary between the CAN transceiver and the communication bus. It introduces additional switching elements and drivers that mediate the signal transitions, controlling the activation and deactivation timing to suppress ringing and electromagnetic interference while allowing high-speed communication

Inventive Principle:
Principle #24Intermediary (Mediator)

2Object-affected harmful factors

If SiC circuit is added to manage transient signals, then ringing and electromagnetic interference are reduced, but device complexity increases

Engineering Contradiction:
Improveringing and electromagnetic interferenceVSAvoidcircuit structure
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The SiC circuit is integrated with the existing CAN transceiver architecture by sharing common components such as power supply terminals, ground references, and control logic. The switching elements and drivers in the SiC circuit are combined with the transceiver's existing structure, reducing the need for completely separate circuitry and minimizing overall device complexity

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The SiC circuit is designed to handle multiple functions within a unified structure: it manages transient signals during state transitions, suppresses ringing, reduces electromagnetic interference, and maintains signal integrity. This multi-functionality is achieved through shared switching elements and drivers that perform multiple roles depending on the operational state

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250392340A1Methods, systems, and apparatus to reduce ringing in a differential output of a transceiver
Publication Date: 2025.12.25 TEXAS INSTRUMENTS INC
  • US20250392340A1 patent drawing
  • US20250392340A1 patent drawing
  • US20250392340A1 patent drawing

AI summary

An example transceiver includes a resistor having a first terminal and a second terminal coupled to a communication bus terminal. The transceiver includes a first transistor having a control terminal, a first terminal coupled to the first terminal of the resistor, and a second terminal coupled to a common mode voltage terminal. The transceiver includes a second transistor having a control terminal, a first terminal coupled to the second terminal of the resistor, and a second terminal coupled to the common mode voltage terminal. The transceiver includes a first driver having a first terminal coupled to a ground terminal, a second terminal coupled to the second terminal of the first transistor and the second terminal of the second transistor, a third terminal coupled to the control terminal of the first transistor, and a fourth terminal coupled to the control terminal of the second transistor.