Multi-Phase DAC CAN Transmitter for Smoother Signal Transitions
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Solution Overview
Problem
CAN transmitters face challenges in generating smooth transitions between output levels due to limited clock speed, which affects their ability to reduce electromagnetic interference, especially in high voltage environments and for higher bit rate specifications like CAN XL, where existing processes are costly and not cost-effective.
Innovation Solution
A CAN transmitter design utilizing a multi-phase clock signal to drive multiple Digital to Analog Converters (DACs), allowing for a higher effective clock frequency and more discrete steps in transitions, resulting in smoother output levels and reduced electromagnetic interference through Gaussian wave shaping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-phase clock signal is used to drive the DAC, then the device complexity is reduced, but the transition smoothness and electromagnetic interference reduction capability deteriorate due to limited clock speed
Solution Approach 1:
The single clock signal is segmented into multiple phases (e.g., 3 phases: φ1, φ2, φ3), each driving a separate DAC. This segmentation allows the system to achieve higher effective clock frequency (3× the original frequency) without requiring a single high-frequency clock, thus maintaining transition smoothness while avoiding excessive device complexity.
Solution Approach 2:
Multiple DAC outputs are merged/combined to form the final smoothed transition waveform. Each DAC contributes a portion of the transition sequence, and their combined output achieves the desired smooth transition that would require a much higher single-clock frequency.
2Manufacturing precision
If the clock frequency is increased to generate smoother transitions, then the transition smoothness improves, but the device complexity and cost increase due to requiring higher frequency processes
Solution Approach 1:
The system uses periodic multi-phase clock signals to drive the DACs in sequence. Each phase operates at a lower frequency, but the periodic switching between phases creates the effect of a higher frequency system, achieving smooth transitions without requiring expensive high-frequency process nodes.
Solution Approach 2:
Instead of using a single high-frequency clock, the system creates multiple copies of the lower-frequency clock signal, each with a different phase offset. These copied and phased clock signals are then used to drive multiple DACs, achieving the equivalent effect of a high-frequency system with lower-cost components.
3Device complexity
If fewer discrete steps are used in the DAC transition, then the device complexity is reduced, but the electromagnetic interference frequency remains in a difficult-to-suppress spectrum
Solution Approach 1:
The system dynamically distributes the transition steps across multiple time phases. Each DAC executes a portion of the transition sequence at a different time, which dynamically spreads the spectral content of the transition and raises the EMI frequency to a more suppressible range.
Data Source
AI summary
A Controller Area Network (CAN) transmitter, in which transitions between output levels are smoothed through use of multiple Digital to Analog Converters (DACs) switched by a multi-phase clock signal. Example embodiments include a CAN transmitter (100) comprising: an oscillator (101) configured to generate a clock signal having n equally spaced phases (clk_0, clk_120, clk_240), where n is an integer greater than 1; n Digital to Analog Converters, DACs (1021-3), each DAC having an input connected to one of the n phases of the clock signal and to a common data input line, each DAC being configured to provide an output signal that transitions between first and second output levels in M discrete steps upon being triggered by a transition of a signal on the data input line synchronized with the one of the n phases of the clock signal; and an output amplifier stage (103) configured to provide a differential CAN output signal from a combination of output signals from each of the n DACs (1021-3).