Multi-Phase DAC CAN Transmitter for Smoother Signal Transitions
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Solution Overview
Problem
Existing CAN transmitters face challenges in generating smooth transitions between output levels, which are necessary to reduce electromagnetic interference, especially at higher bit rates like CAN XL, without requiring more expensive high-frequency processes.
Innovation Solution
A CAN transmitter design utilizing multiple Digital to Analog Converters (DACs) switched by a multi-phase clock signal, allowing for a greater number of discrete steps in transitions between output levels, thereby smoothing the transitions and reducing electromagnetic interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a single-phase clock signal is used to drive DACs, then the device complexity is low, but the transition smoothness is insufficient leading to electromagnetic interference
Solution Approach 1:
The patent divides the single clock signal into multiple phase-shifted clock signals (e.g., 3 phases at 120 degrees apart). Each phase drives a separate DAC, creating segmented transitions that collectively form a smoother overall transition. This segmentation of the clocking function reduces electromagnetic interference while maintaining manageable device complexity through systematic phase distribution.
Solution Approach 2:
The patent employs periodic phase-shifted clock signals to drive the DACs in a cyclic manner. Each DAC is activated at a specific phase angle, creating a periodic sequence of transitions. This periodic action distributes the transition events over time, reducing peak electromagnetic interference while maintaining continuous operation.
2Object-affected harmful factors
If more discrete steps are used to smooth transitions, then electromagnetic interference is reduced, but the clock frequency requirement increases beyond process capabilities
Solution Approach 1:
Instead of increasing clock frequency in the time domain, the patent introduces a phase dimension by using multiple clock phases. This transforms the problem from requiring faster transitions to achieving smoother transitions through parallel phased operations. The effective transition resolution becomes n times the original clock frequency through phase distribution, not through frequency multiplication.
Solution Approach 2:
The patent segments the transition process into multiple phase-staggered steps, where each DAC contributes a portion of the overall transition. This segmentation allows the system to achieve fine-grained transition control equivalent to a much higher frequency clock without actually requiring that high frequency, as each DAC operates at the base clock frequency but at different phase offsets.
3Manufacturing precision
If multiple phase-shifted DACs are used to achieve smooth transitions, then transition smoothness improves, but the device complexity increases
Solution Approach 1:
The patent uses identical DAC circuits for each phase, making each DAC a universal building block that performs the same function with the same characteristics. This universality simplifies design and manufacturing, as the same circuit template is replicated n times rather than designing n different circuits. The multi-functionality comes from these identical DACs operating at different phases to collectively achieve the smooth transition function.
Solution Approach 2:
The patent segments the smooth transition function across multiple identical DAC units, each handling a specific phase portion of the transition. This functional segmentation allows the complex task of creating smooth transitions to be distributed across simpler, identical building blocks, reducing the complexity burden on any single component while achieving the overall precision goal.
Data Source
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AI summary
The disclosure relates to a Controller Area Network (CAN) transmitter, in which transitions between output levels are smoothed through use of multiple Digital to Analog Converters (DACs) switched by a multi-phase clock signal. Example embodiments include a CAN transmitter (100) comprising: an oscillator (101) configured to generate a clock signal having n equally spaced phases (clk_0, clk_120, clk_240), where n is an integer greater than 1; n Digital to Analog Converters, DACs (1021-3), each DAC having an input connected to one of the n phases of the clock signal and to a common data input line, each DAC being configured to provide an output signal that transitions between first and second output levels in M discrete steps upon being triggered by a transition of a signal on the data input line synchronized with the one of the n phases of the clock signal; and an output amplifier stage (103) configured to provide a differential CAN output signal from a combination of output signals from each of the n DACs (1021-3).