CAN-XL Message Handler Partitioning for Low-Latency Data Transfer
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Solution Overview
Problem
Implementing a message-based protocol like CAN-XL primarily in hardware results in large size and high cost, while implementing it in software fails to meet data rate requirements, leading to issues with message transmission speed and integrity.
Innovation Solution
A hardware and software partitioned architecture for the message handler, where a software-implemented message handler processor manages transmit and receive data memories, utilizing hardware-implemented message handler core circuitry for priority-based message transmission and buffering, with a hardware transmit FIFO to meet timing requirements without increasing device size or cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If message-based protocol interface is implemented primarily in hardware, then data transmission speed and reliability are improved, but device size and manufacturing cost increase
Solution Approach 1:
The message handler is divided into two distinct components: hardware-implemented core circuitry that handles protocol-specific functions (message buffering, priority decoding, transmission control) and software-implemented processor that handles data management. This segmentation allows critical timing functions to be performed in hardware while keeping overall device size manageable through software handling of less time-critical operations.
Solution Approach 2:
A shared memory interface acts as an intermediary between the hardware message handler core and the software message handler processor. This intermediary enables efficient data exchange without requiring direct complex hardware-software integration, thus maintaining device simplicity while achieving high-speed communication through the hardware component.
2Device complexity
If message-based protocol interface is implemented primarily in software, then device size and cost are reduced, but data transmission speed and timing requirements are not met
Solution Approach 1:
The message handler is divided into two distinct components: hardware-implemented core circuitry that handles protocol-specific functions (message buffering, priority decoding, transmission control) and software-implemented processor that handles data management. This segmentation allows critical timing functions to be performed in hardware while keeping overall device size manageable through software handling of less time-critical operations.
Solution Approach 2:
Different parts of the message handling system are implemented with different qualities: the time-critical protocol control functions are implemented in hardware for high-speed operation, while the data management functions are implemented in software for flexibility and reduced device complexity. This local differentiation optimizes both speed and device size.
3Reliability
If hardware message handler core circuitry is used, then message transmission timing and priority handling are improved, but manufacturing cost increases
Solution Approach 1:
The message handler is divided into two distinct components: hardware-implemented core circuitry that handles protocol-specific functions (message buffering, priority decoding, transmission control) and software-implemented processor that handles data management. This segmentation allows critical timing functions to be performed in hardware while keeping overall device size manageable through software handling of less time-critical operations.
Solution Approach 2:
The hardware message handler core circuitry is designed to be protocol-agnostic and can handle multiple message-based protocols through configurable parameters, making it a universal component that can be reused across different applications. This multi-functionality reduces the need for multiple specialized hardware components, thereby reducing manufacturing costs while maintaining high reliability.
Data Source
AI summary
Apparatuses and computer-implemented methods for implementing a message-based protocol interface with a communication bus are provided. An example apparatus for implementing a message-based protocol interface with a communication bus may include message handler core circuitry having a transmit message buffer, wherein the transmit message buffer is configured to store a portion of a transmit message. The apparatus may further include receive handler circuitry configured to store a portion of a received message. The apparatus further includes a message handler processor comprising a processor and an instruction memory including program code, the instruction memory and program code configured to, with the processor, cause the message handler processor to transmit at least the portion of the transmit message from a transmit data memory to the message handler core circuitry and receive the received message from the receive handler circuitry into a receive data memory.


