CAN-XL Message Handler Hardware–Software Partitioning for Low Latency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Implementing a message-based protocol like CAN-XL primarily in hardware results in large and expensive devices, while implementing it in software fails to meet data rate requirements, leading to issues such as overwritten, dropped, and corrupt messages.
Innovation Solution
A hardware and software partitioned architecture for the message handler, where a software-implemented message handler processor manages transmit and receive data memories, utilizing hardware-implemented message handler core circuitry with priority decoding and FIFO mechanisms to ensure timely message transmission without increasing device size or cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the message handler is implemented primarily in hardware, then the data rate requirements are met, but the device size and cost increase significantly
Solution Approach 1:
The message handler is divided into two distinct parts: a hardware message handler core that performs critical real-time functions (priority decoding, FIFO management, message buffering) and a software message handler processor that handles higher-level protocol operations. This segmentation allows the hardware portion to be optimized for speed while the software portion provides flexibility, resolving the contradiction between meeting data rate requirements and avoiding excessive device size.
Solution Approach 2:
A shared memory space acts as an intermediary between the hardware message handler core and the software message handler processor. The hardware core writes to and reads from this shared memory, allowing the software processor to access message data without direct hardware integration. This intermediary approach enables the system to achieve high data rates through hardware while keeping the overall device size manageable by avoiding complete hardware implementation.
2Device complexity
If the message handler is implemented in software, then the device size is reduced, but the data rate requirements are not met and messages are overwritten or dropped
Solution Approach 1:
By segmenting the message handler into hardware and software components, the critical real-time message handling functions are offloaded to hardware, ensuring reliable message transmission at high data rates. The software component handles protocol-level operations where reliability is maintained through proper memory management and synchronization mechanisms in the shared memory interface.
Solution Approach 2:
The hardware message handler core performs preliminary actions by pre-decoding priorities, pre-managing FIFO queues, and pre-buffering messages before they are processed by the software handler. This preliminary processing ensures that messages are ready for timely transmission, preventing overwriting and dropping while maintaining reliable message integrity.
3Reliability
If hardware message handler core circuitry is added to meet data rate requirements, then message transmission reliability improves, but the device cost increases
Solution Approach 1:
The message handler is segmented such that only the essential real-time functions are implemented in hardware (priority decoding, FIFO management, message buffering), while the rest of the functionality is handled by software. This selective hardware implementation achieves the required message transmission reliability without the need for a complete hardware solution, thereby controlling device cost.
Solution Approach 2:
The patent uses a cost-effective approach by implementing the message handler as a hybrid system where the hardware core provides reliable real-time processing and the software processor provides flexible protocol handling. This hybrid approach is more economical than a complete hardware implementation while maintaining the necessary reliability, effectively using a mix of hardware and software resources to achieve the goal.
Data Source
AI summary
Apparatuses and computer-implemented methods for implementing a message-based protocol interface with a communication bus are provided. An example apparatus for implementing a message-based protocol interface with a communication bus may include message handler core circuitry having a transmit message buffer, wherein the transmit message buffer is configured to store a portion of a transmit message. The apparatus may further include receive handler circuitry configured to store a portion of a received message. The apparatus further includes a message handler processor comprising a processor and an instruction memory including program code, the instruction memory and program code configured to, with the processor, cause the message handler processor to transmit at least the portion of the transmit message from a transmit data memory to the message handler core circuitry and receive the received message from the receive handler circuitry into a receive data memory.