CAN XL Transceiver Simplification for Low-Cost Bus Communication
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Solution Overview
Problem
Existing CAN XL communication systems are costly for subscriber stations that require only simple functions, such as indicator lights or sensors, due to their high complexity and demand for precise components like high-precision clocks and protocol controllers.
Innovation Solution
A transceiver design for CAN XL systems that eliminates the dominant bus state, reduces circuit complexity, and omits high-precision clocks and arbitration, allowing for a CAN XL transceiver with reduced functionality and lower costs, enabling communication with high error robustness, higher bit rates, and larger data packets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If CAN XL communication is implemented with full functionality, then bit rate and data transmission capability are improved, but device cost and complexity increase
Solution Approach 1:
The patent extracts and removes the dominant bus state functionality from the CAN XL transceiver, keeping only the recessive bus state. This extraction eliminates the need for complex dominant state control logic while maintaining the high bit rate capability through edge-triggered sampling, thereby resolving the contradiction between speed and device complexity
Solution Approach 2:
The patent employs a simplified transceiver design that uses basic digital logic components (D-flip-flops, AND gates, OR gates) instead of complex protocol controllers and high-precision clocks. This approach uses cheaper, simpler components that can be easily replaced or updated, achieving high bit rate communication without the cost and complexity of full CAN XL functionality
2Reliability
If CAN XL transceiver with full functionality is used, then communication reliability is improved, but manufacturing cost increases
Solution Approach 1:
The patent replaces expensive high-precision clock circuits and protocol controllers with simple digital logic components that are cheaper to manufacture. The design uses standard D-flip-flops and logic gates that can be mass-produced at lower cost while maintaining communication reliability through edge-triggered sampling and differential signaling
Solution Approach 2:
The patent changes the operational parameters by eliminating the dominant bus state and using only the recessive bus state with edge-triggered sampling. This parameter change simplifies the transceiver design and reduces manufacturing costs while maintaining reliable communication through the inherent noise immunity of differential signaling and edge-triggered detection
3Device complexity
If simplified transceiver design is used, then device cost is reduced, but error robustness may be compromised
Solution Approach 1:
The patent converts the potential harm of simplified design into a benefit by using edge-triggered sampling that is inherently robust to noise and interference. The differential signaling and edge-triggered detection mechanism transforms simple digital logic into a reliable communication system that maintains error robustness despite the reduced complexity of the transceiver design
Data Source
AI summary
A transceiver for a commander or responder subscriber station of a serial bus system. The transceiver includes a transmitter module for sending a digital transmission signal based on a frame for a message to be sent via the bus as a differential signal to a bus of the bus system, a receiver module for receiving a differential signal from the bus and for generating a digital reception signal from the differential signal received from the bus and for forwarding the digital reception signal to a communication control device for evaluating the digital reception signal using a predetermined frame for a message from the bus, and an operating mode switching module for switching the transmitter module and the receiver module into a first operating mode between messages on the bus or into a second or third operating mode for sending or receiving a message.