Canonical Form Layout Pattern Verification
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Solution Overview
Problem
Current design rule checking (DRC) processes struggle with complex geometric shapes, leading to checking errors and inefficiencies in identifying problematic configurations in IC design layouts, especially as feature sizes shrink and complexity increases, and there is a gap between traditional logic-based diagnosis tools and the needs of failure analysis and yield engineers.
Innovation Solution
The development of pattern-aware physical verification techniques that transform and determine canonical forms of layout patterns, allowing for pattern matching and grouping of rotation, mirror, translation, and scale variants to simplify the identification of problematic configurations and improve diagnosis accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional design rule checking processes are used, then checking simplicity is maintained, but checking accuracy deteriorates for complex geometric shapes
Solution Approach 1:
The patent segments complex geometric shapes into multiple simplified geometric primitives (rectangles, polygons, circles, arcs). Each primitive can be independently checked against design rules using simple 1D checks, yet collectively they accurately represent and verify complex shapes, resolving the contradiction between checking accuracy and process complexity.
2Productivity
If feature size is reduced to increase circuit density, then productivity is improved, but manufacturing precision deteriorates
Solution Approach 1:
The patent transitions from representing shapes as single complex polygons to representing them as collections of 2D geometric primitives with explicit boundary definitions. This dimensional expansion in representation allows precise control of shape boundaries at reduced feature sizes, improving manufacturing precision while maintaining high circuit density.
3Measurement precision
If complex shapes are manually verified, then checking accuracy is maintained, but productivity deteriorates
Solution Approach 1:
The patent replaces manual visual verification with an automated computational system that decomposes complex shapes into geometric primitives and applies algorithmic 1D checking rules. This substitution maintains verification accuracy through systematic boundary checking while dramatically improving productivity by eliminating manual inspection of complex geometries.
4Reliability
If design rules are derived from failure analysis, then reliability is improved, but loss of time increases
Solution Approach 1:
The patent enables design rules to be established earlier in the design flow by using geometric primitive decomposition and 1D checking during the layout design phase itself, rather than waiting for post-fabrication failure analysis. This preliminary verification action maintains reliability by catching issues early while reducing time loss by eliminating iterative failure analysis cycles.
Data Source
AI summary
Aspects of the disclosed technology relate to techniques for determining expanded canonical forms of layout patterns. Coordinates of vertices of geometric elements in a window of a layout design are first transformed into new coordinates of the vertices, wherein the coordinates of vertices do not comprise clipped coordinates and the transforming comprises: performing a translation on the coordinates of vertices based on differences between maximum and minimum X/Y coordinate values of the vertices. Based on sums of X/Y coordinate values of the new coordinates of the vertices, a canonical form of the geometric elements is determined. The canonical form coordinates of the vertices for a plurality of windows may then be determined. The plurality of windows comprise the window, are centered in the same location as the window, and have different sizes.