Canonical Layout Pattern Matching for IC Design Rule Checking
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Solution Overview
Problem
Current design rule checking (DRC) processes struggle with accurately verifying complex geometric shapes in IC layout designs, leading to manufacturing issues and inefficiencies, as they rely on abstracted and derived representations rather than visual patterns, and traditional diagnosis tools lack precision in identifying layout pattern-related defects.
Innovation Solution
The method involves transforming coordinates of geometric elements in a layout design into new coordinates, determining a canonical form based on sums of X and Y values, and applying symmetry operations to simplify pattern matching, enabling more efficient physical verification and diagnosis by grouping identical, rotated, mirrored, or scaled layout patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional design rule checking processes are used to verify complex geometric shapes, then the checking process can be performed, but the accuracy of verification deteriorates leading to manufacturing issues
Solution Approach 1:
The patent creates a copied and transformed representation of the layout pattern by generating canonical forms through coordinate transformations. Instead of directly analyzing complex geometric shapes in their original form, the system creates simplified copies (canonical forms) that preserve essential pattern characteristics while eliminating variability. This copying approach enables accurate pattern matching and verification without the complexity of the original shapes, resolving the contradiction between verification accuracy and manufacturing reliability.
Solution Approach 2:
The patent applies parameter changes by transforming coordinates of geometric elements through mathematical operations (translation, rotation, scaling) to generate canonical forms. By changing the parameter representation of layout patterns from their original complex coordinates to standardized canonical coordinates, the system achieves consistent and accurate pattern recognition. This parameter transformation resolves the verification accuracy issue while maintaining manufacturing reliability through standardized pattern matching.
2Device complexity
If abstracted and derived representations are used in design rule checking, then the checking process can be simplified, but the accuracy of complex shape verification deteriorates
Solution Approach 1:
The system creates a copied representation (canonical form) that is simpler than the original complex geometric shapes but retains all essential pattern information needed for verification. This copied form uses standardized coordinate systems and normalized representations, reducing checking process complexity while maintaining shape verification accuracy through precise pattern matching algorithms.
Solution Approach 2:
The patent segments the verification process into distinct stages: generating canonical forms from original patterns, storing these canonical forms in a database, and performing pattern matching queries. This segmentation allows each stage to be optimized independently - the canonical form generation simplifies complexity, while the pattern matching stage maintains high verification accuracy through systematic comparison.
3Productivity
If traditional diagnosis tools are used to identify layout pattern defects, then defect detection can be performed, but the precision of defect identification deteriorates
Solution Approach 1:
The patent creates canonical form copies of defective patterns that can be stored and compared against a database of known good and bad patterns. This copying approach enables precise defect identification by comparing the canonical form of the suspected defect against stored reference patterns, significantly improving identification precision while maintaining high productivity through automated database querying and matching.
Data Source
AI summary
Aspects of the disclosed technology relate to techniques for determining canonical forms of layout patterns. Coordinates of vertices of geometric elements in a window of a layout design are first transformed into new coordinates of the vertices, wherein the coordinates of vertices do not comprise clipped coordinates and the transforming comprises: performing a translation on the coordinates of vertices based on differences between maximum and minimum X/Y coordinate values of the vertices. Based on sums of X/Y coordinate values of the new coordinates of the vertices, a canonical form of the geometric elements is determined. The canonical form coordinates of the vertices may then be determined and sorted. The sorted canonical form coordinates may be employed for pattern matching.