Canonical Timing Model Superposition for Statistical Static Timing Analysis
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Solution Overview
Problem
Conventional statistical static timing analysis (SSTA) requires separate processing for each corner of interest, which can be inefficient as it does not account for unprocessed corners and lacks consideration of second-order terms like process and temperature variations simultaneously.
Innovation Solution
The method involves defining a canonical delay model with statistical variables and a transformation matrix to project timing values to unprocessed corners, allowing for the superposition of canonical delay models and consideration of second-order terms, enabling efficient timing analysis across various parameter spaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate processing is performed for each corner of interest in conventional SSTA, then timing analysis can be performed for each specific condition, but computational efficiency deteriorates and unprocessed corners are not accounted for
Solution Approach 1:
The patent merges multiple corner-specific timing analyses into a unified canonical timing model that processes all corners simultaneously. By defining n statistical variables that represent multiple corners and using a transformation matrix to project canonical delays to any corner, the system combines what would otherwise require separate processing into a single efficient operation that accounts for all corners of interest.
Solution Approach 2:
The canonical timing model serves as a universal representation that can be transformed to any corner of interest through the transformation matrix. This multi-functional approach allows the same canonical model to provide timing analysis for any corner condition without requiring separate processing for each corner, thereby improving computational efficiency while maintaining accuracy.
2Device complexity
If conventional SSTA processes only specific corners, then processing is simpler, but the analysis lacks consideration of second-order terms like process and temperature variations simultaneously
Solution Approach 1:
The patent changes the parameter representation from corner-specific values to canonical statistical variables that capture second-order effects. By defining n statistical variables for each node and edge and using a transformation matrix that incorporates scale factors representing different conditions (process, temperature, etc.), the system transforms the analysis to simultaneously consider multiple second-order variations while maintaining manageable processing complexity.
3Productivity
If canonical delay models are projected to unprocessed corners using transformation matrices, then computational resources are reduced, but the method requires defining statistical variables and transformation matrices
Solution Approach 1:
The patent performs preliminary action by defining the canonical delay models with statistical variables and constructing the transformation matrix before the actual timing analysis. This upfront setup, while requiring initial effort, enables all subsequent corner projections to be performed efficiently through simple matrix operations, thereby reducing computational resources for the main analysis task.
Data Source
AI summary
A system and method to perform timing analysis in integrated circuit development involves defining an integrated circuit design as nodes representing components of the integrated circuit design that are interconnected by edges representing wires. Sequentially connected nodes define a path. Statistical variables are defined for a canonical delay model of each node and edge of the integrated circuit design and define a first set of conditions. The method includes performing a statistical static timing analysis to obtain an arrival time at each node as a sum of the canonical delay models for nodes and edges that precede the node in the path of the node, obtaining a projected arrival time at a second set of conditions for the node by scaling the arrival time for the node using scale factors that represent the second set of conditions and using a transformation matrix, and providing the integrated circuit design for fabrication.