Wiring Substrate Cantilever Pad Absorbs Thermal Stress

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Solution Overview

Problem

High-performance semiconductor chips are vulnerable to thermal stress due to differences in thermal expansion coefficients between the wiring substrate and the semiconductor chip, leading to potential deterioration in performance and reliability of semiconductor devices.

Innovation Solution

A wiring substrate with a cantilever structure is created by forming recess portions under the pad wiring layers, allowing the connection pads to act as aerial wirings that move vertically like a spring, absorbing thermal stress and improving electrical connection reliability. This is achieved by forming recesses in the insulating layer, filling a sacrifice layer, and removing it selectively to create a hollow portion under the pad wiring layers after flip-chip mounting the semiconductor chip.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a rigid wiring substrate structure is used, then manufacturing simplicity is maintained, but thermal stress causes semiconductor chip deterioration

Engineering Contradiction:

Improvesemiconductor chip performanceVSAvoidwiring substrate structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The pad wiring layer is designed with a cantilever structure that allows dynamic movement in the thickness direction. This dynamic flexibility enables the wiring substrate to absorb thermal expansion differences between the substrate and semiconductor chip, preventing stress-induced chip deterioration while maintaining manufacturing feasibility through a structured approach.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The pad wiring layer is segmented into multiple regions with different flexibility characteristics. The region under the semiconductor chip has greater flexibility to absorb stress, while other regions maintain structural integrity. This segmentation allows differential movement patterns that protect the chip without requiring complete structural redesign.

Inventive Principle:

Principle #1Segmentation

2Reliability

If the pad wiring layer is made flexible to absorb thermal stress, then chip protection is improved, but wiring layer structural stability deteriorates

Engineering Contradiction:

Improvethermal stress absorptionVSAvoidwiring layer structure

Core Design Contradiction:

ReliabilityVSStability of the object's composition

Solution Approach 1:

Different regions of the pad wiring layer are assigned different flexibility properties. The region positioned under the semiconductor chip is designed with higher flexibility to absorb thermal stress, while other regions maintain greater structural stability. This local differentiation allows the wiring layer to simultaneously provide stress absorption where needed and structural support where required.

Inventive Principle:

Principle #3Local quality

3Reliability

If a hollow portion is created under the pad wiring layer, then thermal stress relaxation is achieved, but manufacturing process complexity increases

Engineering Contradiction:

Improvestress relaxationVSAvoidmanufacturing process

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The hollow portion is formed in advance during the wiring substrate manufacturing process, before semiconductor chip mounting. This preliminary creation of the hollow structure integrates stress relaxation functionality into the base substrate fabrication, avoiding the need for additional post-assembly modifications and reducing overall manufacturing complexity.

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The cantilever structure effectively relaxes thermal stress and enhances the reliability of electrical connections, protecting high-performance semiconductor chips from stress-induced performance deterioration and ensuring sufficient reliability of the semiconductor device.

Implementation Method 1

removing it selectively from the insulating layer and the pad wiring layer to form a hollow portion

Methodology Applied

Scientific EffectSelective removal:

Implementation Method 2

a coefficient of thermal expansion is different between the wiring substrate 100 (a resin, a copper wiring, or the like) and the semiconductor chip (silicon chip) 600. Therefore, a thermal stress is generated when a heat is applied to the semiconductor device

Methodology Applied

Scientific EffectThermal expansion: Thermal Expansion

Implementation Method 3

the pad wiring portion is formed as an aerial wiring... the cantilever structure in which the pad wiring portion is formed as an aerial wiring

Methodology Applied

Scientific EffectElastic deformation: Elasticity

Data Source

PatentUS7893524B2Wiring substrate and semiconductor device and method of manufacturing the same

Publication Date: 2011.02.22 SHINKO ELECTRIC IND CO LTD

AI summary

In a wiring substrate of a semiconductor device, a hollow portion is provided under a pad wiring portion including a connection pad, and thus a wiring layer has a cantilever structure in which the pad wiring portion is formed as an aerial wiring, and a semiconductor chip is flip-chip connected to the connection pad. The pad wiring portion including the connection pad is formed on a sacrifice layer which is filled in a recess portion in an interlayer insulating layer of the wiring substrate, then the semiconductor chip is flip-chip connected to the connection pad, and then the hollow portion is provided by removing the sacrifice layer.