Cap Layer on Epitaxial Layer for FinFET Stress Uniformity
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Solution Overview
Problem
In the fabrication of semiconductor devices, particularly in non-planar metal-oxide semiconductor (MOS) transistors like fin field effect transistors (FinFETs), achieving an even epitaxial layer shape is challenging, which affects device performance due to the difficulty in obtaining uniform stress across the channel region.
Innovation Solution
A method involving the formation of a substrate with a gate structure, a recess adjacent to the gate, an epitaxial layer with a V-shaped profile, and a cap layer on top, where the cap layer's surface is higher than the substrate surface, using silicon phosphide with varying phosphorus concentrations to improve the epitaxial layer's shape and prevent excessive loss during contact plug formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If selective epitaxial growth (SEG) technique is used to form epitaxial structure, then carrier mobility is increased through stress application, but the epitaxial layer cannot obtain an even shape affecting device performance
Solution Approach 1:
The epitaxial structure is segmented into multiple functional layers: a first epitaxial layer for stress induction, a second epitaxial layer for shape planarization, and a cap layer for final uniformity. This segmentation allows each layer to fulfill its specific function without compromising the others, resolving the contradiction between stress-induced carrier mobility enhancement and shape uniformity.
Solution Approach 2:
Different regions of the epitaxial structure are assigned different material compositions and thicknesses to achieve local optimization. The first epitaxial layer has specific composition for stress, while the second layer and cap layer are optimized for shape control. This local quality differentiation enables simultaneous achievement of stress-induced mobility improvement and overall shape uniformity.
2Speed
If epitaxial layer is formed to induce stress in channel region, then speed of MOS transistor is improved, but the epitaxial layer shape becomes uneven during fabrication
Solution Approach 1:
The first epitaxial layer is formed preliminarily to establish the stress-inducing structure, followed by the formation of the second epitaxial layer and cap layer that perform preliminary planarization before subsequent fabrication steps. This preliminary action sequence ensures that stress is established early while shape uniformity is prepared in advance for contact plug formation.
Solution Approach 2:
The epitaxial structure uses composite material layers with different compositions - silicon germanium for stress induction and silicon carbide for shape control - allowing the structure to simultaneously provide both mechanical stress for high-speed operation and geometric uniformity for proper device fabrication.
3Force
If conventional epitaxial growth is used, then stress can be applied to channel, but excessive loss of epitaxial layer occurs during contact plug formation
Solution Approach 1:
The cap layer is formed beforehand to cushion and protect the underlying epitaxial layers during contact plug formation. This protective layer prevents excessive loss of the stress-inducing epitaxial material while allowing the contact plug to be formed through the cap layer, thus preserving the integrity of the epitaxial structure.
Solution Approach 2:
The cap layer serves as an intermediary between the contact plug formation process and the underlying epitaxial layers. It mediates the mechanical and chemical interactions during fabrication, protecting the valuable epitaxial material from excessive loss while still allowing necessary processing to occur.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the V-shaped profile of the epitaxial layer, ensuring even stress distribution and improving the performance of semiconductor devices by maintaining the epitaxial layer integrity during contact plug formation.
Implementation Method 1
selective epitaxial growth (SEG) technique to form epitaxial structure such as silicon germanium (SiGe) epitaxial layer in a silicon substrate
Data Source
AI summary
A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a gate structure is formed on the substrate. Next, a recess is formed adjacent to two sides of the gate structure, and an epitaxial layer is formed in the recess, in which a top surface of the epitaxial layer is lower than a top surface of the substrate. Next, a cap layer is formed on the epitaxial layer, in which a top surface of the cap layer is higher than a top surface of the substrate.