Cap Layer Protects Epitaxial Layer in MOS Transistor Fabrication
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Solution Overview
Problem
Current methods for forming MOS transistors with epitaxial layers often damage the surface during contact hole formation, affecting device performance due to the sequence of removing interlayer dielectric layers and depositing metals.
Innovation Solution
A method involving forming a cap layer with a top surface even with or lower than the substrate surface, within a contact hole, to protect the epitaxial layer and improve fabrication processes for semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the interlayer dielectric layer is removed and metals are deposited to form contact plugs, then the contact hole is formed for electrical connection, but the surface of the epitaxial layer is damaged and device performance is affected
Solution Approach 1:
A cap layer is formed over the epitaxial layer before the contact hole formation process. This cap layer serves as a protective barrier that prevents damage to the epitaxial layer surface during subsequent interlayer dielectric removal and metal deposition steps, while still allowing the contact hole to be formed for electrical connection.
2Speed
If selective epitaxial growth is used to form SiGe or SiC layers, then carrier mobility is increased and transistor speed is improved, but the fabrication process becomes more complex and the epitaxial layer surface is vulnerable to damage
Solution Approach 1:
The cap layer is formed in advance before contact hole processing, providing protection to the carefully grown epitaxial layer. This preliminary protective measure simplifies the overall fabrication process by preventing the need for additional repair or protection steps after contact hole formation, while maintaining the speed benefits of the epitaxial layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the integrity of the epitaxial layer and reduces damage during contact hole formation, thereby improving the performance and reliability of semiconductor devices by maintaining the epitaxial layer's integrity.
Implementation Method 1
it has been common in the conventional art to use selective epitaxial growth (SEG) technique to form epitaxial structure such as silicon germanium (SiGe) epitaxial layer in a silicon substrate
Data Source
AI summary
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming an epitaxial layer adjacent to the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a first contact hole in the ILD layer adjacent to the gate structure; and forming a cap layer in the recess, in which a top surface of the cap layer is even with or lower than a top surface of the substrate.